Method and apparatus for modular circuit design for a programmable logic device

• US 7,600,210 B1
• Filed: 09/28/2005
• Issued: 10/06/2009
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Mason, Jeffrey M., Young, Jay T.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Lin; Aric
• Application Number:
  US11/238,433
• Time in Patent Office: 1,469 Days
• Field of Search: 716/16
• US Class Current: 716/138
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Method, apparatus, and computer readable medium for modular circuit design for a programmable logic device (PLD) is described. In one example, a circuit design is captured. The circuit design includes a plurality of modules and one or more logic interface macros positioned on a floorplan. Each of the plurality of modules is one of a static module or a reconfigurable module. The one or more logic interface macros include programmable logic of the PLD and are positioned at one or more boundaries between one or more pairs of the plurality of modules. Each of the plurality of modules is implemented using information generated from the capturing step. The modules are assembled using the information generated from the capturing step and implementing step. Routing for a static module can cross a defined implementation area for a reconfigurable module, and a static module can be placed anywhere outside of reconfigurable module areas.

Claims

1. A method of modular circuit design for an integrated circuit (IC), comprising:

capturing a circuit design having plurality of modules and one or more logic interface macros positioned on a floorplan, each of the plurality of modules being one of a static module or a reconfigurable module, each of the one or more logic interface macros;

being positioned at a boundary between a module pair of the plurality of modules; and

comprising one or more configurable logic block (CLB) slices having a plurality of pins, a first half of the plurality of pins being located within a first module of the module pair and coupled only to ports of the first module, and a second half of the plurality of pins being located within a second module of the module pair and coupled only to ports of the second module;

implementing each of the plurality of modules using information generated from the capturing step; and

assembling the plurality of modules using the information generated from the capturing step and information generated from the implementing step.

2. The method of claim 1, wherein each of the one or more logic interface macros comprises at least one routing resource of the IC.

3. The method of claim 1, wherein the plurality of modules includes at least one reconfigurable module having a defined area in the floorplan that is less than a full height of the IC.

4. The method of claim 3, wherein the plurality of modules includes at least one static module, the at least one static module being positioned an unused area in the floorplan above or below the defined area.

5. The method of claim 1, wherein the step of implementing comprises:

implementing each static module of the plurality of modules using at least one routing resource in a reconfigurable area of the floorplan;

recording the at least one routing resource in a list of used routing resources; and

implementing each reconfigurable module of the plurality of modules using the list of used routing resources.

6. The method of claim 1, wherein the step of implementing comprises:

mapping each of the plurality of modules onto physical resources in the IC; and

placing and routing each of the plurality of modules.

7. The method of claim 1, wherein the step of assembling comprises:

combining the plurality of modules to produce at least one full design implementation file; and

generating at least one design implementation file for at least one flavor of each reconfigurable module of the plurality of modules.

8. The method of claim 7, wherein each of the at least one full design implementation file comprises each static module and a flavor of each reconfigurable module of the plurality of modules.

9. The method of claim 7, wherein each of the at least one design implementation file comprises each static module and a flavor of a single reconfigurable module of the plurality of modules.

10. A system for modular circuit design for an integrated circuit (IC), comprising:

a logic capture tool for capturing a circuit design having plurality of modules, each of the plurality of modules being one of a static module or a reconfigurable module;

a floorplan tool for positioning the plurality of modules and positioning one or more logic interface macros on a floorplan, each of the one or more logic interface macros;

being positioned at a boundary between a module pair of the plurality of modules; and

comprising one or more configurable logic block (CLB) slices having a plurality of pins, a first half of the plurality of pins being located within a first module of the module pair and coupled only to ports of the first module, and a second half of the plurality of pins being located within a second module of the module pair and coupled only to ports of the second module;

an implementation tool for implementing each of the plurality of modules and assembling the plurality of modules using information generated from the logic capture tool and the floorplan tool.

11. The system of claim 10, wherein each of the one or more logic interface macros comprises at least one routing resource of the IC.

12. The system of claim 10, further comprising:

a synthesis tool for synthesizing the circuit design.

13. The system of claim 10, wherein the implementation tool comprises:

a map tool for mapping each of the plurality of modules onto physical resources of the IC;

a place and route tool for placing and routing each of the plurality of modules; and

a bitstream generator for generating at least one implementation file for the circuit design.

14. The system of claim 13, wherein the place and route tool is configured to place and route at least one static module of the plurality of modules using at least one routing resource in a reconfigurable area of the floorplan and to record the at least one routing resource in a list of used routing resources.

15. The system of claim 14, wherein the place and route tool is configured to place and route at least one reconfigurable module of the plurality of modules in the reconfigurable area using the list of used routing resources.

16. The system of claim 13, wherein the at least one implementation file comprises at least one full design implementation file and at least one design implementation file, each of the at least one full design implementation file comprising each static module and a flavor of each reconfigurable module of the plurality of modules, each of the at least one design implementation file comprising each static module and a flavor of a single reconfigurable module of the plurality of modules.

17. The system of claim 10, wherein the information generated from the logic capture tool and the floorplan tool comprises constraint data.

18. A computer readable medium having stored thereon software for modular circuit design for an integrated circuit (IC), the software comprising:

code for capturing a circuit design having plurality of modules and one or more logic interface macros positioned on a floorplan, each of the plurality of modules being one of a static module or a reconfigurable module, each of the one or more logic interface macros;

being positioned at a boundary between a module pair of the plurality of modules; and

comprising one or more configurable logic block (CLB) slices having a plurality of pins, a first half of the plurality of pins being located within a first module of the module pair and coupled only to ports of the first module, and a second half of the plurality of pins being located within a second module of the module pair and coupled only to ports of the second module;

code for implementing each of the plurality of modules using information generated from the code for capturing; and

code for assembling the plurality of modules using the information generated from the code for capturing and information generated from the code for implementing.