System surface for decoding coded data

• US 7,600,688 B2
• Filed: 06/23/2008
• Issued: 10/13/2009
• Est. Priority Date: 04/02/2004
• Status: Expired due to Fees

• Current Assignee: Silverbrook Research Pty Limited
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia, Lapstun, Paul
• Primary Examiner(s): Lee; Seung H
• Application Number:
  US12/144,593
• Publication Number:
  US 20080283610A1
• Time in Patent Office: 477 Days
• Field of Search: 235/375, 235/435, 235/439, 235/462.25, 235/462.28, 235/487
• US Class Current: 235/462.28
• CPC Class Codes: G06K 19/06037 multi-dimensional coding

Abstract

A system for decoding coded data provided on or in a surface is provided. The coded data includes at least one data portion arranged on or in the surface and alignment data at least partially indicative of at least one clock indicator. The system includes a sensor which senses data provided in a sensing region and a decoder. The sensor senses at least part of the alignment data and at least part of the at least one data portion. The decoder determines, using the sensed alignment data part, the clock indicator, updates, using the clock indicator, a PLL, determines, using the PLL, a relative position between the sensing region and the at least one sensed data portion part, and at least partially decodes, using the relative position, the at least one data portion part.

Claims

1. A system for decoding coded data provided on or in a surface, the coded data including:

at least one data portion arranged on or in the surface; and

, alignment data at least partially indicative of at least one clock indicator;

the system including;

a sensor which senses data provided in a sensing region, the sensor sensing;

at least part of the alignment data; and

,

at least part of the at least one data portion;

a decoder for;

determining, using the sensed alignment data part, the clock indicator;

updating, using the clock indicator, a phase-locked loop (PLL);

determining, using the PLL, a relative position between the sensing region and the at least one sensed data portion part; and

,

at least partially decoding, using the relative position, the at least one data portion part.

2. A system according to claim 1, wherein the decoder is for:

determining the position of at least one marker to determine a gross registration;

determining, using the gross registration, a clock indicator in a clock track;

updating, using the clock indicator, an alignment PLL;

determining, using the alignment PLL, a fine registration of the coded data in the alignment direction.

3. A system according to claim 1, wherein the coded data includes a registration structure, the registration structure including at least two clock tracks indicative of a position of the coded data in the direction perpendicular to the alignment direction and two alignment lines for each clock track, the two alignment lines being indicative of the position of the respective clock track, and wherein the decoder is for:

determining, using an alignment PLL, a position of the alignment lines for a respective clock track;

determining, using the position of the alignment lines, the position of each respective clock track; and

,

updating the alignment PLL.

4. A system according to claim 3, wherein the decoder is for:

for each clock track, determining, using a respective data clock PLL, a position of a clock indicator on the clock track;

determining, using the position of the clock indicator on each clock track, an alignment angle; and

,

updating each data clock PLL.

5. A system according to claim 1, wherein the decoder is for decoding the coded data by:

determining a transform for a scan line using the alignment data, the transform being indicative of coordinates of bit encoding locations within the data portions; and

,

detecting bit values using the transform.

6. A system according to claim 5, wherein the decoder is for:

determining coordinates of sample values from the coordinates of the bit-encoding location; and

,

determining a bit-encoding value by interpolating sample values from two successive scan lines.

7. A system according to claim 6, wherein the decoder is for:

assigning a temporary value to a decoded bitstream bit which has more than two possible values;

resolving a binary value for the bit based on the values of surrounding bits in the data-encoding area; and

,

writing resolved encoded bitstream bit values to a storage device in bitstream order.

8. A system according to claim 1, wherein the decoder is for:

detecting a pilot feature in the alignment data, the pilot feature being detected at least two locations;

determining, using the pilot feature;

an alignment angle between a scanline direction and an alignment direction; and

,

an initial registration in a direction perpendicular to the alignment direction;

detecting a registration marker in a registration feature in the alignment data;

determining, using the registration marker, a gross registration in the alignment direction;

detecting, using the gross registration, a registration clock indicator in the alignment data;

determining, using the registration clock indicator, a fine registration in the alignment direction;

detecting, using the fine registration and the alignment angle and the initial registration, at least one alignment line;

updating, using the at least one detected alignment line, the fine registration;

determining, using the updated fine registration, the position of two data clock tracks in the alignment data;

detecting, using the position of the data clock tracks, a data clock indicator on each data clock track;

determining, using each data clock indicator, an updated alignment angle and an updated registration in a direction perpendicular to the alignment direction;

detecting at least part of the at least one data portion; and

,

decoding, using the updated alignment angle and the fine registration and the updated registration, at least some of the at least one detected data portion part.

9. A system according to claim 8, wherein the decoder is for, repeatedly:

detecting the at least one alignment line;

updating the fine registration;

determining using the updated fine registration and the updated registration, the position of the data clock tracks;

detecting a data clock indicator on each data clock track;

updating the updated alignment angle and the updated registration; and

,

detecting at least part of the at least one data portion, to thereby allow the at least one data portion to be decoded.

10. A system according to claim 8, the decoder is for:

detecting, at two locations in the pilot feature, a clock indicator;

synchronising a respective pilot PLL with each clock indicator to thereby track the pilot feature;

determining, using the pilot PLLs;

the alignment angle; and

,

the initial registration;

initialising, using the initial registration and the alignment angle, two data clock PLLs;

detecting the registration marker in the alignment data;

determining, using the registration marker, the gross registration;

synchronising, using the gross registration, a registration PLL with the registration clock indicator in the alignment data to thereby track the registration feature;

determining, using the registration PLL, the fine registration;

initialising, using the fine registration, two alignment PLLs;

synchronising the alignment PLLs with alignment markers to thereby track the data clock tracks;

determining, using the alignment PLLs, the position of two data clock tracks in the alignment data;

detecting, using the position of the data clock tracks, a data clock indicator on each data clock track;

synchronising each data clock PLL with a corresponding data clock indicator to thereby track the registration of the data in the direction perpendicular to the alignment direction; and

,

determining, using the data clock PLLs, at least one of;

the updated alignment angle; and

,

the position of coded data on the surface.