Surround gate access transistors with grown ultra-thin bodies

• US 7,601,595 B2
• Filed: 11/07/2006
• Issued: 10/13/2009
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): SMITH, MATTHEW S
• Application Number:
  US11/557,224
• Publication Number:
  US 20070066019A1
• Time in Patent Office: 1,071 Days
• Field of Search: 438/268, 257/E21.375, 257/E21.645, 257/E21.626, 257/E21.621, 257/E21.66
• US Class Current: 438/268
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Claims

1. A method of forming transistor structures comprising:

forming a pillar vertically extending from a surface of a substrate;

growing a single crystalline semiconductive transistor body to extend vertically around the pillar;

forming a surround gate structure around the transistor body;

forming a source region adjacent lower portions of the transistor body;

forming a drain region adjacent an upper portion of the transistor body; and

forming a multiple grain region adjacent the upper portion of the single crystalline body so as to extend across a top of the pillar and wherein the drain region is formed to at least partially occupy the multiple grain region.

2. The method of claim 1, wherein growing the single crystalline transistor body comprises performing a solid phase epitaxial growth process.

3. The method of claim 1, further comprising forming a first conductor in the surface of the substrate and wherein the pillar and body are formed offset from the first conductor so as partially overlie the first conductor with a remainder extending beyond the first conductor.

4. The method of claim 3, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

5. A method of forming transistor structures comprising:

forming a vertical extension from a surface;

growing a single crystalline semiconductive transistor body to extend vertically around the vertical extension;

forming a surround gate structure around the transistor body;

forming a source region adjacent lower portions of the transistor body;

forming a drain region adjacent an upper portion of the transistor body; and

forming a multiple grain region adjacent the upper portion of the single crystalline body so as to extend across a top of the vertical extension.

6. The method of claim 5 wherein the drain region is formed to at least partially occupy the multiple grain region.

7. The method of claim 5, wherein growing the single crystalline transistor body comprises performing a solid phase epitaxial growth process.

8. The method of claim 5, further comprising forming a first conductor in the surface of the substrate and wherein the vertical extension and body are formed offset from the first conductor so as to partially overlie the first conductor with a remainder extending beyond the first conductor.

9. The method of claim 8, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

10. The method of claim 9, wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

11. A method of forming transistor structures comprising:

forming a vertical extension from a surface;

growing a crystalline semiconductive transistor body to extend vertically around the vertical extension;

forming a surround gate structure around the transistor body;

forming a source region at lower portions of the transistor body;

forming a drain region at an upper portion of the transistor body; and

forming a multiple grain region at the upper portion of the crystalline body so as to extend across a top of the vertical extension.

12. The method of claim 11 wherein the drain region is formed to at least partially occupy the multiple grain region.

13. The method of claim 11, wherein growing the crystalline transistor body comprises performing a solid phase epitaxial growth process.

14. The method of claim 11, further comprising forming a first conductor in the surface and wherein the vertical extension and body are formed offset from the first conductor so as partially overlie the first conductor with a remainder extending beyond the first conductor.

15. The method of claim 14, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

16. The method of claim 15, wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

17. A method of forming transistor structures comprising:

forming a pillar vertically extending from a surface of a substrate;

growing a single crystalline semiconductive transistor body to extend vertically around the pillar;

forming a surround gate structure around the transistor body;

forming a source region adjacent lower portions of the transistor body;

forming a drain region adjacent an upper portion of the transistor body; and

forming a first conductor in the surface of the substrate wherein the pillar and body are formed offset from the first conductor so as partially overlie the first conductor with a remainder extending beyond the first conductor.

18. The method of claim 17, wherein growing the single crystalline transistor body comprises performing a solid phase epitaxial growth process.

19. The method of claim 17, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

20. A method of forming transistor structures comprising:

forming a vertical extension from a surface;

growing a single crystalline semiconductive transistor body to extend vertically around the vertical extension;

forming a surround gate structure around the transistor body;

forming a source region adjacent lower portions of the transistor body;

forming a drain region adjacent an upper portion of the transistor body; and

forming a first conductor in the surface of the substrate and wherein the vertical extension and body are formed offset from the first conductor so as to partially overlie the first conductor with a remainder extending beyond the first conductor.

21. The method of claim 20 wherein the drain region is formed to at least partially occupy the multiple grain region.

22. The method of claim 20, wherein growing the single crystalline transistor body comprises performing a solid phase epitaxial growth process.

23. The method of claim 20, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

24. The method of claim 23, wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

25. A method of forming transistor structures comprising:

forming a vertical extension from a surface;

growing a crystalline semiconductive transistor body to extend vertically around the vertical extension;

forming a surround gate structure around the transistor body;

forming a source region at lower portions of the transistor body;

forming a drain region at an upper portion of the transistor body; and

forming a first conductor in the surface and wherein the vertical extension and body are formed offset from the first conductor so as partially overlie the first conductor with a remainder extending beyond the first conductor.

26. The method of claim 25 wherein the drain region is formed to at least partially occupy the multiple grain region.

27. The method of claim 25, wherein growing the crystalline transistor body comprises performing a solid phase epitaxial growth process.

28. The method of claim 25, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.

29. The method of claim 28, wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.