Semiconductor device and method for forming the same

• US 7,602,020 B2
• Filed: 09/18/2006
• Issued: 10/13/2009
• Est. Priority Date: 10/09/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Teramoto, Satoshi, Takemura, Yasuhiko, Zhang, Hongyong
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/522,376
• Publication Number:
  US 20070007529A1
• Time in Patent Office: 1,121 Days
• Field of Search: 257/66, 257/72, 257/347, 257/E27.111
• US Class Current: 257/347
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A thin film transistor device reduced substantially—in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film.

Claims

1. A semiconductor device comprising:

a semiconductor layer formed on an insulating surface;

a pair of first impurity regions formed in the semiconductor layer;

a pair of second impurity regions formed between the pair of first impurity regions;

a channel region formed between the pair of second impurity regions;

a pair of metal silicide regions formed on the pair of first impurity regions;

a gate insulating film formed over the semiconductor layer;

a gate electrode formed over the gate insulating film;

a pair of side walls adjacent to the gate electrode;

a first insulating film formed on upper and side surfaces of the gate electrode and between the gate electrode and the pair of side walls;

a second insulating film formed over the gate electrode, the first insulating film and the pair of side walls; and

an electrode formed over the second insulating film and electrically connected to one of the pair of metal silicide regions.

2. A semiconductor device according to claim 1, wherein the first insulating film comprises an oxide of the gate electrode.

3. A semiconductor device according to claim 1, wherein the first insulating film comprises an anodic oxide of the gate electrode.

4. A semiconductor device according to claim 1, wherein the semiconductor layer has a thickness of 500 angstrom or less.

5. A semiconductor device according to claim 1, wherein the pair of metal silicide regions is in contact with the pair of first impurity regions and the pair of second impurity regions.

6. A semiconductor device comprising:

a semiconductor layer formed over an insulating substrate;

a pair of first impurity regions formed in the semiconductor layer;

a pair of second impurity regions formed between the pair of first impurity regions;

a channel region formed between the pair of second impurity regions;

a pair of metal silicide regions formed on the pair of first impurity regions;

a gate insulating film formed over the semiconductor layer;

a gate electrode formed over the gate insulating film;

a pair of side walls adjacent to the gate electrode;

a first insulating film formed on upper and side surfaces of the gate electrode and between the gate electrode and the pair of side walls;

a second insulating film formed over the gate electrode, the first insulating film and the pair of side walls; and

an electrode formed over the second insulating film and electrically connected to one of the pair of metal silicide regions.

7. A semiconductor device according to claim 6, wherein the first insulating film comprises an oxide of the gate electrode.

8. A semiconductor device according to claim 6, wherein the first insulating film comprises an anodic oxide of the gate electrode.

9. A semiconductor device according to claim 6, wherein the semiconductor layer has a thickness of 500 angstrom or less.

10. A semiconductor device according to claim 6, wherein the pair of metal silicide regions is in contact with the pair of first impurity regions and the pair of second impurity regions.

11. A semiconductor device according to claim 6, wherein the insulating substrate is a glass substrate.

12. A semiconductor device comprising:

a semiconductor layer formed on an insulating surface;

a pair of impurity regions formed in the semiconductor layer;

a channel region formed between the pair of impurity regions;

a pair of metal silicide regions formed in contact with the pair of the impurity regions and extended throughout entire thickness of the semiconductor layer;

a gate insulating film formed over the semiconductor layer;

a gate electrode formed over the gate insulating film;

a pair of side walls adjacent to the gate electrode;

a first insulating film formed on upper and side surfaces of the gate electrode and between the gate electrode and the pair of side walls;

a second insulating film formed over the gate electrode, the first insulating film and the pair of side walls; and

an electrode formed over the second insulating film and electrically connected to one of the pair of metal silicide regions.

13. A semiconductor device according to claim 12, wherein the first insulating film comprises an oxide of the gate electrode.

14. A semiconductor device according to claim 12, wherein the first insulating film comprises an anodic oxide of the gate electrode.

15. A semiconductor device according to claim 12, wherein the semiconductor layer has a thickness of 500 angstrom or less.

16. A semiconductor device according to claim 12, wherein the pair of metal silicide regions is in contact with the insulating surface.

17. A semiconductor device comprising:

a semiconductor layer formed over an insulating substrate;

a pair of impurity regions formed in the semiconductor layer;

a channel region formed between the pair of impurity regions;

a pair of metal silicide regions formed in contact with the pair of the impurity regions and extended throughout entire thickness of the semiconductor layer;

a gate insulating film formed over the semiconductor layer;

a gate electrode formed over the gate insulating film;

a pair of side walls adjacent to the gate electrode;

a first insulating film formed on upper and side surfaces of the gate electrode and between the gate electrode and the pair of side walls;

a second insulating film formed over the gate electrode, the first insulating film and the pair of side walls; and

an electrode formed over the second insulating film and electrically connected to one of the pair of metal silicide regions.

18. A semiconductor device according to claim 17, wherein the first insulating film comprises an oxide of the gate electrode.

19. A semiconductor device according to claim 17, wherein the first insulating film comprises an anodic oxide of the gate electrode.

20. A semiconductor device according to claim 17, wherein the semiconductor layer has a thickness of 500 angstrom or less.

21. A semiconductor device according to claim 17, wherein the pair of metal silicide regions is in contact with the insulating substrate.

22. A semiconductor device according to claim 17, wherein the insulating substrate is a glass substrate.