Semiconductor component and method of manufacture

• US 7,602,027 B2
• Filed: 12/29/2006
• Issued: 10/13/2009
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Shastri, Sudhama C., Burke, Peter A., Hose, Sallie
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US11/618,363
• Publication Number:
  US 20080157217A1
• Time in Patent Office: 1,019 Days
• Field of Search: None
• US Class Current: 257/379
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a substrate, wherein providing the substrate includes forming a resistor from or above the substrate;

forming a capacitor at a first level above the substrate by;

forming a first layer of dielectric material over the substrate;

forming a first layer of conductive material over the first layer of dielectric material, the first layer of conductive material comprising aluminum and having first and second portions;

forming a second layer dielectric material over the first layer of conductive material; and

forming a second layer of conductive material over the second layer of dielectric material, the second layer of conductive material comprising aluminum; and

forming an inductor at a second level above the first level by;

forming a third layer of dielectric material over the second layer of conductive material;

forming at least one damascene opening in the third layer of dielectric material by;

forming a fourth layer of dielectric material on the third layer of dielectric material;

forming a first portion of the at least one damascene opening in the third layer of dielectric material; and

forming a second portion of the at least one damascene opening in the fourth layer of dielectric material, wherein the second portion of the at least one damascene opening exposes a portion of the second layer of conductive material;

forming copper in the at least one damascene opening and further including;

forming an active device from the substrate;

forming an opening in the first layer of dielectric material, the opening exposing the active device;

forming an electrical conductor in the opening;

forming the second portion of the first layer of conductive material on the conductor;

electrically isolating the first portion of the first layer of conductive material from the second portion of the first layer of conductive material; and

forming a trench through the second, third and fourth layers of dielectric material, the trench exposing the second portion of the first layer of conductive material.

2. The method of claim 1, further including forming a conductive material in the trench.

3. The method of claim 2, wherein forming the conductive material in the trench includes forming copper in the trench.

4. The method of claim 3, further including forming aluminum over the copper in the trench.