Using programmable latch to implement logic

• US 7,602,213 B2
• Filed: 12/26/2007
• Issued: 10/13/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Tier Logic, Inc.
• Inventors: Dorairaj, Nij
• Primary Examiner(s): Le; Don P
• Application Number:
  US11/964,084
• Publication Number:
  US 20090167347A1
• Time in Patent Office: 657 Days
• Field of Search: 326 37- 41, 326/46, 326/112, 326/119, 326/121, 326 93- 98
• US Class Current: 326/38
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input.

Claims

1. A latch adapted to implement AND logic in a field programmable gate array (FPGA), comprising:

a storage element having an output reflecting a stored data state;

a first logic input coupled to the storage element to store the data state;

a global control signal in the FPGA coupled to the storage element to change the stored data state; and

a second logic input programmably coupled to the global control signal to generate an AND output from the first and second logic inputs,

wherein the storage element comprises a latch with the AND output as part of the FPGA.

2. The latch of claim 1, wherein the storage element comprises a latch.

3. The latch of claim 2, comprising a multiplexer coupling the global control signal to the latch.

4. The latch of claim 3, comprising a local logic signal coupled to an input of the multiplexer.

5. The latch of claim 1, wherein the first logic input is an output generated by a programmable logic block.

6. The latch of claim 5, comprising a multiplexer coupled to the programmable logic block and the storage element.

7. The latch of claim 5, wherein the programmable logic block comprises one or more of:

look-up-table (LUT), multiplexer circuit, NAND gate, NOR gate, AND gate, OR gate, XOR gate, product-term, register, processor, and Arithmetic-Logic-Unit.

8. A method of adapting a latch to implement a logic function, the method comprising:

coupling a first logic input to an input of the latch used for storing a data state in the latch; and

providing a configurable element to couple a second logic signal to a global control signal used for globally changing the stored data state in the latch, wherein , when the configurable element is programmed to couple the second logic input to the global control signal, the output generates a logic function of the first and second logic inputs.

9. The method of claim 8, wherein the logic function comprises one of:

AND function, OR function, NAND function, NOR function, NOT function.

10. The method of claim 8, comprising multiplexing the global control signal to the latch.

11. The method of claim 10, comprising providing a local signal to an input of the multiplexer.

12. The method of claim 8, comprising coupling a logic block to the storage element.

13. The method of claim 12, comprising multiplexing the output of the logic block to the storage element.

14. The method of claim 12, comprising providing one or more of:

look-up-table (LUT), multiplexer circuit, NAND gate, NOR gate, AND gate, OR gate, XOR gate, product-Term , register, processor, and Arithmetic-Logic-Unit.

15. A logic circuit, comprising:

a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a first logic function of the plurality of logic inputs; and

a latch having;

a first latch input to store a data state coupled to said at least one output of logic block;

a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and

a latch output, wherein when the local input is coupled to the global latch input, the latch output generates a second logic function of the logic output and the local input.

16. The logic circuit of claim 15, wherein the logic function comprises one of:

AND function, OR function, NAND function, NOR function, NOT function.

17. The logic circuit of claim 15, comprising a multiplexer coupling the global control signal to the latch.

18. The logic circuit of claim 17, comprising a local signal coupled to an input of the multiplexer.

19. The logic circuit of claim 15, comprising a logic block coupled to the latch.

20. The logic circuit of claim 19, comprising a multiplexer coupled to the logic block and the storage element.

21. The logic circuit of claim 19, wherein the logic block comprises one or more of:

look-up-table (LUT), multiplexer circuit, NAND gate, NOR gate, AND gate, OR gate, XOR gate, product-term, register, processor, and Arithmetic-Logic-Unit.

22. The logic circuit of claim 19, wherein the latch output generates a logic function of the logic block output and one or more latch inputs.

23. The logic circuit of claim 22, wherein the logic function comprises an AND operation.

24. A programmable logic device, comprising:

a programmable logic output of one or more primary programmable inputs; and

a secondary programmable input; and

a latch having the programmable logic output and the secondary programmable input coupled to the latch to generate a logic function of the primary and secondary inputs.