Reconfigurable sequencer structure

• US 7,602,214 B2
• Filed: 04/07/2008
• Issued: 10/13/2009
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/082,073
• Publication Number:
  US 20080191737A1
• Time in Patent Office: 554 Days
• Field of Search: 326 37- 41, 326/46
• US Class Current: 326/38
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components

Abstract

A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

Claims

1. A cell element field for data processing, comprising:

a function cell arrangement adapted for executing at least one of algebraic and logic functions; and

a memory cell arrangement adapted for at least one of receiving, storing, and outputting information;

wherein;

function-cell/memory-cell combinations are formed in which a control connection leads from the function cell arrangement to the memory cell arrangement; and

backward registers, which are situated in an information path between the memory cell arrangement and function cell arrangement, are assigned to at least one of (a) at least one memory cell of the memory cell arrangement and (b) at least one function cell of the function cell arrangement.

2. The cell element field as recited in claim 1, wherein:

the cell element field forms at least one of a processor, coprocessor, and microcontroller; and

cells of at least one of the function cell arrangement and the memory cell arrangement are at least one of reconfigurable and preselectable in at least one of their function and interconnection.

3. The cell element field as recited in one of the preceding claim 1, wherein the function arrangement includes cells formed as arithmetic logic units.

4. The cell element field as recited in claim 3, wherein the arithmetic logic units are formed as extended ALUs.

5. The cell element field as recited in claim 1, wherein the memory cell arrangement includes at least one of cells designed as volatile data memories and cells designed as and nonvolatile data memories.

6. The cell element field as recited in claim 1, wherein the memory cell arrangement includes cells designed for storage of at least one of data to be processed and program steps to be executed.

7. The cell element field as recited in claim 1, wherein the memory cell arrangement includes memory cells designed for, in response to triggering by a function cell of the function cell arrangement which controls the memory cells, sending stored information at least one of directly and indirectly to a bus leading to the function cell.

8. The cell element field as recited in claim 1, wherein at least one input-output arrangement is assigned to a function-cell/memory-cell combination for at least one of sending information to and receiving information from at least one of an external unit another function cell, another function-cell/memory-cell combination, and a memory cell.

9. The cell element field as recited in claim 8, wherein the at least one input-output arrangement is also designed to receive control commands from the function cell arrangement.

10. The cell element field as recited in claim 1, wherein at least one of (a) a controller is designed to transmit, and (b) at least one of a memory cell and an input-output cell is designed to decode, at least some a DATA WRITE/READ command, an ADDRESS POINTER WRITE/READ command, a PROGRAM POINTER WRITE/READ command, a PROGRAM POINTER INCREMENT command, a STACK POINTER WRITE/READ command, a PUSH command, a POP command, an OPCODE command, and a FETCH command.

11. The cell element field for data processing as recited in claim 1, wherein a function cell of the function cell arrangement is situated adjacent to at least one of (a) at least one memory cell and (b) at least one input-output cell.

12. The cell element field as recited in claim 1, wherein cell elements of the function cell and memory cell arrangements are arranged multidimensionally, in a matrix, such that at least one of a function cell, an adjacent memory cell, and an input-output cell is able to receive data from an upper row and output data into a lower row via buses.

13. A cell element field for data processing, comprising:

a function cell arrangement adapted for executing at least one of algebraic and logic functions; and

a memory cell arrangement adapted for at least one of receiving, storing, and outputting information;

wherein;

function-cell/memory-cell combinations are formed in which a control connection leads from the function cell arrangement to the memory cell arrangement and

a memory cell of the memory cell arrangement is adapted to receive information from at least one of (a) a function cell, of the function cell arrangement, which controls the memory cell, (b) an input-output cell, and (c) a cell having an arithmetic logic unit that does not control the memory cell.

14. A cell element field for data processing, comprising:

a function cell arrangement adapted for executing at least one of algebraic and logic functions; and

a memory cell arrangement adapted for at least one of receiving, storing, and outputting information;

wherein;

function-cell/memory-cell combinations are formed in which a control connection leads from the function cell arrangement to the memory cell arrangement; and

a function cell of the function cell arrangement, as the sole master, is adapted to access at least one of a control connection and a bus segment functioning as the control connection.

15. A Field Programmable Gate Array (FPGA) chip, comprising:

at least some coarse granular data processing cells at least for processing algebraic functions, each of the at least some coarse granular data processing cells being reconfigurable in at least one of interconnection and function at runtime without interfering with others of the data processing cells not being reconfigured; and

at least some data memory cells for storing processing data;

wherein;

at least some of the data memory cells are physically separated from the data processing cells and are adapted for storing commands for at least one of the data processing cells; and

at least some of the data processing cells are adapted for receiving commands from the data memory cells at runtime.

16. The FPGA chip according to claim 15, further comprising:

an arrangement for transmitting commands, at runtime, from at least one of the data memory cells to at least one of the data processing cells whose execution is thereby defined.

17. The FPGA chip according to claim 15, wherein a combination of at least one of the data processing cells with at least one of the data memory cells is adapted for being clocked at a higher frequency than surrounding cells.

18. The FPGA chip according to claim 15, wherein the data memory cells are adapted for altering a command sequence for the at least one of the data processing cells by receiving data during runtime.

19. The FPGA chip according to claim 15, wherein at least some of the data memory cells are non-volatile.

20. The FPGA chip according to claim 15, wherein the at least some data memory cells are adapted for storing commands and data for the at least some of the data processing cells.

21. A Field Programmable Gate Array (FPGA) chip, comprising:

at least some coarse granular data processing cells at least for processing algebraic functions, each of the at least some coarse granular data processing cells being reconfigurable in at least one of interconnection and function at runtime without interfering with others of the data processing cells not being reconfigured;

at least some data memory cells adapted for storing processing data and for storing commands; and

an arrangement for transmitting commands from at least one of the data memory cells to at least one of the data processing cells for defining an execution of the at least one of the data processing cells at runtime;

wherein at least some of the data memory cells are physically separated from the data processing cells.

22. The FPGA chip according to claim 21, wherein a combination of at least one of the data processing cells with at least one of the data memory cells is adapted to be clocked at a higher frequency than surrounding cells.

23. The FPGA chip according to claim 21, wherein the data memory cells are adapted for altering a command sequence for the at least one of the data processing cells by receiving data during runtime.

24. The FPGA chip according to claim 21, wherein at least some of the data memory cells are non-volatile.

25. The FPGA chip according to claim 21, wherein the at least some data memory cells are adapted for storing commands and data for at least some of the data processing cells.

26. A Field Programmable Gate Array (FPGA) chip, comprising:

at least some coarse granular data processing cells at least for processing algebraic functions, each of the at least some coarse granular data processing cells being reconfigurable in at least one of interconnection and function at runtime without interfering with others of the data processing cells not being reconfigured; and

at least some data memory cells for storing processing data;

wherein;

at least some of the data memory cells are physically separated from the processing cells; and

at least some of the data processing cells and at least some of the data memory cells are adapted for being connected to form a sequencer structure.

27. The FPGA chip according to claim 26, wherein the at least some of the data memory cells are adapted for supplying commands to be executed to the at least some of the data processing cells at runtime.

28. The FPGA chip according to claim 26, wherein a combination of at least one of the data processing cells with at least one of the data memory cells is adapted to be clocked at a higher frequency than surrounding cells.

29. The FPGA chip according to claim 26, wherein the data memory cells are adapted for altering a command sequence for at least one of the data processing cells by receiving data during runtime.

30. The FPGA chip according to claim 26, wherein at least some of the data memory cells are non-volatile.

31. The FPGA chip according to claim 26, wherein the at least some data memory cells are adapted for storing commands and data for the at least some of the data processing cells.

32. A method for implementing a sequencer in a Field Programmable Gate Array (FPGA) chip, the FPGA chip comprising:

at least some coarse granular data processing cells at least for processing algebraic functions, each of the at least some coarse granular data processing cells being reconfigurable in at least one of interconnection and function at runtime without interfering with others of the data processing cells not being reconfigured; and

at least some data memory cells for storing processing data, the at least some data memory cells being physically separated from the at least some data processing cells;

wherein at least one of the data memory cells is connected to, and provides commands to be executed to, at least one of the data processing cells.

33. The method according to claim 32, wherein at least one of the data memory cells is connected to exactly one of the data processing cells for providing commands to be executed by the exactly one of the data processing cells.

34. The method according to any one of claims 32 and 33, wherein an arrangement is implemented to control the at least some data memory cells.

35. The method according to any one of claims 32 and 33, wherein the at least one data memory cell stores the commands, and at least some of the data memory cells store data for at least some of the data processing cells.

36. The method according to claim 35, wherein a combination of at least one of the data processing cells with at least one of the data memory cells is adapted for being clocked at a higher frequency than surrounding cells.