Delay-locked loop circuit and method of generating multiplied clock therefrom

• US 7,602,223 B2
• Filed: 10/23/2007
• Issued: 10/13/2009
• Est. Priority Date: 11/21/2006
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Seung-Hwan, Lee, Seung-Won
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Cole; Brandon S
• Application Number:
  US11/877,187
• Publication Number:
  US 20080116950A1
• Time in Patent Office: 721 Days
• Field of Search: 327/116, 327/141, 327144-163, 331/1.A, 331 15- 17, 375373-376
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling a level of a voltage signal in response to the detection signal; and a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal using the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal. The multiplied clock signal is generated by multiplying the external clock signal an integer number of times and the feedback clock signal is delayed from the plurality of delay clock signals by a cycle period of the external clock signal.

Claims

1. A delay-locked loop circuit comprising:

a phase detector generating a detection signal by detecting a phase difference between an external clock signal and a feedback clock signal;

a charge pump controlling a level of a voltage signal VCON in response to the detection signal;

a frequency detector detecting the frequency domain of the external clock signal; and

a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal by means of the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal,

wherein the voltage-controlled delay line operates by dividing the detected frequency domain into two or more frequency domains relative to reference frequencies, and

wherein the multiplied clock signal is generated by multiplying the external clock signal an integer number of times and wherein the feedback clock signal is delayed from the plurality delay clock signals by a cycle period of the external clock signal,

wherein the detection signal of the phase detector includes up and down signals,

wherein the voltage-controlled delay line generates the plurality of delay clock signals using a plurality of delay cells,

wherein the voltage-controlled delay line comprises 2m delay cells (m is a positive integer), sequentially generates 2m delay clock signals with predetermined delay times each through a respective one of the plurality of delay cells, and determines to generate the multiplied clock signal by means of m delay clock signals or 2m delay clock signals, according to a delayed sequence, in response to a selection signal,

wherein the m delay clock signals are used when the external clock signal has a high frequency, and 2m delay clock signals are used when the external clock signal has a low frequency, as determined by the frequency detector,

wherein the voltage-controlled delay line comprises;

a first multiplied clock generator operating to generate a first multiplied clock signal by means of the m-numbered delay clock signals sequentially delayed from the external clock;

a second multiplied clock generator operating to generate a second multiplied clock signal by means of the 2m-numbered delay clock signals; and

a multiplied clock selector operating to select one of the first and second multiplied clock signals in response to the selection signal.

2. The delay-locked loop circuit as set forth in claim 1, wherein the voltage-controlled delay line further comprises:

a plurality of buffers temporarily storing the 2m-numbered delay clock signals,

wherein the delay clock signals stored in the plurality of buffers are transferred to the first and second multiplied clock generators.

3. The delay-locked loop circuit as set forth in claim 1, wherein the first and second multiplied clock generators operate to generate the second multiplied clock signal that is a half of the external clock signal in cycle period.

4. The delay-locked loop circuit as set forth in claim 3, wherein m is 4 and the delay clock signals are generated from a first to an eighth in sequence.

5. The delay-locked loop circuit as set forth in claim 4, wherein the first multiplied clock generator comprises:

a first logic circuit executing an XOR operation with a first and second delay clock signals;

a second logic circuit executing an XOR operation with a third and fourth delay clock signals; and

a third logic circuit generating the first multiplied clock signal by executing an XOR operation with output values of the first and second logic circuits.

6. The delay-locked loop circuit as set forth in claim 5, wherein the second multiplied clock generator comprises:

a fourth logic circuit executing an XOR operation with a fifth and sixth delay clock signals;

a fifth logic circuit executing an XOR operation with a seventh and eighth clock signals;

a sixth logic circuit executing an XOR operation with output values of the fourth and fifth logic circuits;

a seventh logic circuit executing an XOR operation with output values of the first multiplied clock generator and the sixth logic circuit; and

a frequency divider generating the second multiplied clock signal by dividing an output value of the seventh logic circuit in half.

7. The delay-locked loop circuit as set forth in claim 4, wherein the voltage-controlled delay line further comprises:

a feedback clock selector operating to select one from the fourth and eighth delay clock signals in response to the selection signal.