Amplifier

• US 7,602,243 B2
• Filed: 10/30/2007
• Issued: 10/13/2009
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Murao, Yoji
• Primary Examiner(s): Mottola; Steven J
• Application Number:
  US11/928,664
• Publication Number:
  US 20080278231A1
• Time in Patent Office: 714 Days
• Field of Search: 330/10, 330/136
• US Class Current: 330/136
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 3/19 with semiconductor devices only

Abstract

An object of the present invention is, in a high-frequency amplifier using a semiconductor device as an amplifying device, to achieve a high efficiency by controlling input/output matching circuits so that they are always optimized, when a bias voltage applied to the semiconductor device is controlled to correspond to an envelope of a signal. The bias voltage that is applied to the semiconductor device for amplification is changed to corresponding to the envelope of the signal using a bias control circuit, control voltages for controlling impedance of input/output matching circuits are created from the bias voltage, and the bias voltage and the control voltages that are used to control the impedance of the input/output matching circuits of semiconductor device 7 are supplied in synchronization with each other. Accordingly, the impedance of the input/output matching circuits is variably controlled so that the circuits always optimized manner, and thereby high efficiency amplification can be accomplished.

Claims

1. An amplifier including a semiconductor device for amplification and an input/output matching circuit for the semiconductor device for amplification, the amplifier being adapted to change a bias voltage supplied to the semiconductor device that corresponds to an envelope of a signal to be amplified, comprising:

means for varying impedance of the input/output matching circuit that corresponds to the envelope in synchronization with the bias voltage,

wherein the means creates a control voltage for varying the impedance of the input/output matching circuit to correspond to the bias voltage, and

wherein the means calculates the control voltage by one of;

using a polynomial approximation technique based on the bias voltage;

by dividing the bias voltage with a resistor.

2. The amplifier according to claim 1, wherein

the means has a table for storing, in advance, the control voltage corresponding to each bias voltage that corresponds to the envelope, and is adapted to read out the control voltage corresponding to this bias voltage with reference to the table.

3. The amplifier according to claim 1, wherein

the matching circuit is a variable phase shifter of an input/output voltage control type.

4. The amplifier according to claim 1, wherein

information about the envelope is extracted from information about amplitude of a digital signal in a baseband signal processing portion in a previous stage.

5. The amplifier according to claim 1, further comprising:

control means for synchronizing timing for applying the signal to be amplified to the semiconductor device with timing for changing the bias voltage and the control voltage.

6. An amplifier including a semiconductor device for amplification and an input/output matching circuit for the semiconductor device for amplification, the amplifier being adapted to change a bias voltage supplied to the semiconductor device that corresponds to an envelope of a signal to be amplified, comprising:

an envelope information extraction portion for extracting the envelope information from a baseband signal, and

a bias control circuit for varying impedance of the input/output matching circuit that corresponds to the envelope information in synchronization with the bias voltage,

wherein the information about the envelope is extracted from information about amplitude of a digital signal in a baseband signal processing portion in a previous stage.

8. The amplifier of claim 6, wherein the bias control circuit creates a control voltage for varying the impedance of the input/output matching circuit to correspond to the bias voltage.

9. The amplifier of claim 8, wherein the bias control circuit calculates the control voltage by using a polynomial approximation technique based on the vias voltage.

10. The amplifier of claim 8, wherein the bias control circuit calculates the control voltage by dividing the bias voltage with a resistor.

11. The amplifier of claim 8, wherein the bias control circuit has a table for storing, in advance, the control voltage corresponding to each bias voltage that corresponds to the envelope, and is adapted to read out the control voltage corresponding to this bias voltage with reference to the table.

7. An amplifier including a semiconductor device for amplification and an input/output matching circuit for the semiconductor device for amplification, the amplifier being adapted to change a bias voltage supplied to the semiconductor device that corresponds to an envelope of a signal to be amplified, comprising:

bias control circuit for varying impedance of the input/output matching circuit that corresponds to the envelope in synchronization with the bias voltage,

wherein the matching circuit is a variable phase shifter of an input/output voltage control type.

12. The amplifier of claim 7, wherein the bias control circuit creates a control voltage for varying the impedance of the input/output matching circuit to correspond to the bias voltage.

13. The amplifier of claim 12, wherein the bias control circuit calculates the control voltage by using a polynomial approximation technique based on the vias voltage.

14. The amplifier of claim 12, wherein the bias control circuit calculates the control voltage by dividing the bias voltage with a resistor.

15. The amplifier of claim 12, wherein the bias control circuit has a table for storing, in advance, the control voltage corresponding to each bias voltage that corresponds to the envelope, and is adapted to read out the control voltage corresponding to this bias voltage with reference to the table.

16. An amplifier to amplify a carrier signal modulated by an envelope signal, the amplifier comprising:

a semiconductor device to amplify the carrier signal modulated by the envelope signal;

an input/output matching circuit for the semiconductor device to amplify the carrier signal modulated by the envelope signal, the amplifier being adapted to change a bias voltage supplied to the semiconductor device, the bias voltage corresponding to the envelope signal; and

,

means for varying impedance of the input/output matching circuit, the impedance corresponding to the envelope signal, the impedance synchronized to the carrier signal, for the carrier signal to be amplified by the semiconductor device by the bias voltage.

17. The amplifier of claim 16, further comprising a bias control circuit to create a control voltage to vary the impedance of the input/output matching circuit to correspond to the bias voltage.

18. The amplifier of claim 17, wherein the bias control circuit is to calculate the control voltage by using a polynomial approximation technique, based on the bias voltage.

19. The amplifier of claim 17, wherein the bias control circuit is to calculate the control voltage by dividing the bias voltage using a resistor.

20. The amplifier of claim 17, wherein the bias control circuit comprises a table to store in advance the control voltage corresponding to each bias voltage that corresponds to the envelope signal, the bias control circuit being adapted to read the control voltage corresponding to the bias voltage by referencing the table.