Metal-metal capacitor and method of making the same

• US 7,602,599 B1
• Filed: 07/09/2008
• Issued: 10/13/2009
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chien-En
• Primary Examiner(s): Ha; Nguyen T
• Application Number:
  US12/170,409
• Time in Patent Office: 461 Days
• Field of Search: 361/303, 361/306.1, 361/306.3, 361/311, 361328-330, 438/250, 438/253, 438/393, 438/396, 257295-296
• US Class Current: 361/303
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/385 Single unit multiple capacitors, e.g. dual capacitor in one coil

Abstract

A method of making a metal-metal capacitor is disclosed, in which a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer are formed in the order over a substrate; an upper capacitor is defined by etching using a first mask, wherein the stop of the etching can be controlled; a lower capacitor is defined by etching using a second mask; and an anti-reflective third mask is formed to cover the surface, and the capacitor border and metal interconnect conductive wire are defined, so as to make a metal-metal capacitor with a stable structure in a wide process window.

Claims

1. A method of making a metal-metal capacitor, comprising:

providing a substrate;

forming, in the order of, a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer over the substrate;

forming a first mask layer covering the third metal layer, patterning the first mask layer to expose a portion of the third metal layer;

etching the portion of the third metal layer exposed and the underlying second dielectric layer using the first mask layer as a mask and allowing the etching to stop at the second dielectric layer while not penetrating therethrough, thereby forming an upper capacitor structure comprising a second metal layer, a second dielectric layer, and a third metal layer;

forming a second mask layer covering the third metal layer and the second dielectric layer, patterning the second mask layer to expose a portion of the second dielectric layer;

etching the portion of the second dielectric layer exposed, the underlying second metal layer and the underlying first dielectric layer using the second mask layer as a mask and allowing the etching to stop at the first dielectric layer while not penetrating therethrough, thereby forming a lower capacitor structure comprising a second metal layer, a first dielectric layer, and a first metal layer;

removing the second mask layer;

forming a third mask layer covering the third metal layer, the second dielectric layer, and the first dielectric layer, patterning the third mask layer to expose a portion of the first dielectric layer, wherein the third mask layer is anti-reflective;

etching the portion of the first dielectric layer exposed, the underlying first metal layer and the substrate using the third mask layer as a mask and allowing the etching to stop at the substrate, thereby forming the border of the metal-metal capacitor and a metal interconnect conductive wire comprising the first metal layer, wherein the metal-metal capacitor is separated from the metal interconnect conductive wire by a trench;

depositing an inter-metal dielectric layer covering the third mask layer and filling the trench, planarizing the inter-metal dielectric layer; and

;

etching the inter-metal dielectric layer and the third mask layer to form at least one via hole on the first metal layer, the second metal layer, and the third metal layer.

2. The method of claim 1, wherein the third mask layer comprises a bottom anti-reflective coating (BARC) layer.

3. The method of claim 1, wherein the third mask layer comprises SiON.

4. The method of claim 1, wherein the first mask layer comprises a photo resist layer.

5. The method of claim 1, wherein the second mask layer comprises a photo resist layer.

6. The method of claim 1, further comprising a step of filling a metal material into the via hole on the first metal layer, the via hole on the second metal layer, and the via hole on the third metal layer to form metal vias.

7. The method of claim 6, further comprising forming a terminal contacting the metal via on the first metal layer and the metal via on the third metal layer for electrically connecting the first metal layer with the third metal layer.

8. A metal-metal capacitor, comprising:

a first metal layer;

a first capacitor dielectric layer disposed on the first metal layer;

a second metal layer stacked on the first capacitor dielectric layer, wherein the first metal layer, the first capacitor dielectric layer, and the second metal layer constitute a lower capacitor structure;

a second capacitor dielectric layer disposed on the second metal layer; and

a third metal layer stacked on the second capacitor dielectric layer, wherein the second metal layer, the second capacitor dielectric layer, and the third metal layer constitute an upper capacitor;

wherein a portion of the first metal layer is covered with a remaining thickness of the first capacitor dielectric layer and a first mask layer in the order, a portion of the second metal layer is covered with a remaining thickness of the second capacitor dielectric layer and a second mask layer in the order, a portion of the third metal layer is covered with a third mask layer, the first mask layer, the second mask layer, and the third mask layer each are anti-reflective.

9. The metal-metal capacitor of claim 8, wherein the first mask layer, the second mask layer, and the third mask layer are identical.

10. The metal-metal capacitor of claim 8, wherein the first mask layer, the second mask layer, and the third mask layer each comprise a bottom anti-reflective coating.

11. The metal-metal capacitor of claim 8, wherein the first mask layer, the second mask layer, and the third mask layer each comprise SiON.

12. The metal-metal capacitor of claim 8, wherein the first metal layer and the third metal layer are electrically connected to a first terminal of the metal-metal capacitor, and the second metal layer is electrically connected to a second terminal of the metal-metal capacitor.

13. The metal-metal capacitor of claim 8, wherein the first metal layer and the third metal layer are electrically connected to a first terminal of the metal-metal capacitor through a first metal via and a third metal via respectively, the second metal layer is electrically connected to a second terminal of the metal-metal capacitor through a second metal via, the first metal via passes through the first mask layer and the first capacitor dielectric layer of the remaining thickness, the second metal via passes through the second mask layer and the second capacitor dielectric layer of the remaining thickness, and the third metal via passes through the third mask layer.

14. The metal-metal capacitor of claim 8, wherein the area of the second metal layer is less than the area of the first metal layer.

15. The metal-metal capacitor of claim 8, wherein the area of the third metal layer is less than the area of the second metal layer.

16. The metal-metal capacitor of claim 8, wherein the second metal layer is thinner than the first metal layer.