Method and apparatus for automatic configuration of multiple on-chip interconnects
First Claim
Patent Images
1. A method comprising:
- an automatic configuration of a plurality of on-chip interconnects of an on-chip network, including,determining a topology of the on-chip network wherein the determined topology is a directed acyclic graph tree or a fully connected graph;
configuring a plurality of bridge agents and core agents in the on-chip interconnects to communicate with each other based on said topology by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect, where a first bridge agent is configured to communicate from a first on-chip interconnect to a second on-chip interconnect;
configuring a system address map of said network, wherein the first bridge agent and the core agents have address matching components inside the agent and check a correctness of an address by matching the address to the system address map; and
configuring a plurality of signals communicated between components in the on-chip network.
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Abstract
A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design.
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Citations
27 Claims
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1. A method comprising:
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an automatic configuration of a plurality of on-chip interconnects of an on-chip network, including, determining a topology of the on-chip network wherein the determined topology is a directed acyclic graph tree or a fully connected graph; configuring a plurality of bridge agents and core agents in the on-chip interconnects to communicate with each other based on said topology by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect, where a first bridge agent is configured to communicate from a first on-chip interconnect to a second on-chip interconnect; configuring a system address map of said network, wherein the first bridge agent and the core agents have address matching components inside the agent and check a correctness of an address by matching the address to the system address map; and configuring a plurality of signals communicated between components in the on-chip network. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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determining a plurality of address maps for a plurality of networks on a chip; determining a network topology for said chip and said plurality of networks as being a directed acyclic graph tree or a fully connected graph; configuring a system address map of said network, wherein bridge and core agents have address matching components inside the agents and check a correctness of an address by matching the address to the system address map; and configuring a plurality of bridge agents and core agents in a plurality of on-chip interconnects in said chip to communicate with each other, by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect. - View Dependent Claims (13, 14)
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8. The method of 7 wherein said bridge agents each has a configuration feature selected from the group consisting of bridge forwarding, component identification, connection identifier support, error handling, interrupt handling, software generated reset, and timeout of requests.
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9. The method of 7 wherein said bridge agents each has an interface feature selected from the group consisting of address space extension, byte enable extension, burst extension, connection identifier extension, data handshake extension, thread extension, write response extension, flag extension, error extension, control extension, and status extension.
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10. The method of 7 wherein an address map of a specific one of said plurality of bridge agents includes an address map of a network to which said specific bridge agent is attached and an address map to all other attached networks.
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11. The method of 10 wherein one or more of said plurality of bridge agents directly connected to each other have mutually exclusive address regions.
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12. The method of 10 wherein said plurality of core agents have address regions that do not overlap.
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15. A method for configuring on-chip network connections, the method comprising:
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configuring one or more bridge agents and core agents in a plurality of on-chip interconnects of an on-chip network to communicate with each other over the interconnects based upon said on-chip network'"'"'s topology being a fully connected graph or a directed acyclic graph tree; configuring and routing flag signals on a per core basis for one or more cores between components in the on-chip network; configuring and routing error signals on a per core basis for one or more cores between components in the on-chip network; configuring said one or more bridge agents with respective address matchers with an address region that covers a region in system address space that encompasses address regions of all core agents that are connected to the on-chip interconnect of which the one or more bridge agents are a part; and configuring and routing reset signals between components in the on-chip network. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. An apparatus comprising:
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a processor that executes instructions; and a memory device that stores said instructions, said instructions comprising; means for automatic configuration of a plurality of on-chip interconnects of an on-chip network, including, means for determining a topology of the on-chip network as being a fully connected graph or a directed acyclic graph; means for configuring a plurality of bridge agents and core agents in the on-chip interconnects to communicate with each other based on said topology by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect; and means for configuring routing of a reset signal between interconnects, from one of the plurality of bridge agents in the on-chip network to another one of the bridge agents. - View Dependent Claims (27)
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Specification