Scalable distributed memory and I/O multiprocessor systems and associated methods
First Claim
1. Apparatus comprising:
- an interconnect to communicatively couple at least one processor with at least one input/output device, the interconnect includingat least one bridge to send and receive transactions between at least one input/output device and at least one processor; and
at least one crossbar coupled to at least one bridge to route transactions;
wherein at least one crossbar switch comprises non-blocking switches having a plurality of ports; and
wherein at least one crossbar supports independent power/on and reset of the ports.
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Abstract
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
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Citations
38 Claims
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1. Apparatus comprising:
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an interconnect to communicatively couple at least one processor with at least one input/output device, the interconnect including at least one bridge to send and receive transactions between at least one input/output device and at least one processor; and at least one crossbar coupled to at least one bridge to route transactions; wherein at least one crossbar switch comprises non-blocking switches having a plurality of ports; and wherein at least one crossbar supports independent power/on and reset of the ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system, comprising:
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at least one processor; at least one input/output device; and at least one interconnect including at least one bridge to send and receive transactions between at least one input/output device and at least one processor; at least one crossbar coupled to at least one bridge to route transactions; and a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. An integrated circuit comprising:
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a crossbar; a bridge communicatively coupled to the crossbar, the bridge to packetize transactions between at least one processor and at least one input/output device in a format that is compatible with the crossbar; and a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge. - View Dependent Claims (23, 24)
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25. A method of operating an apparatus including at least one processor, at least one input/output device, and at least one interconnect component communicatively coupling at least one processor and at least one input/output device, the method comprising:
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at least one interconnect component utilizing at least two bridges to send and receive transactions between at least one processor and at least one input/output device; and at least one interconnect component utilizing at least two crossbar switches to route the transactions over a bus between at least two bridges. - View Dependent Claims (26, 27)
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28. Apparatus comprising:
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an interconnect to communicatively couple at least one processor with at least one input/output device, the interconnect including at least one bridge to send and receive transactions between at least one input/output device and at least one processor; at least one crossbar coupled to at least one bridge to route transactions; and a plurality of mapping registers communicatively coupled to at least one bridge, the mapping registers to provide routing information for the at least one bridge; wherein a clock for at least one crossbar has a source that is independent of a clock for at least one processor. - View Dependent Claims (29, 30, 31)
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32. Apparatus comprising:
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an interconnect to communicatively couple at least one processor with at least one input/output device, the interconnect including at least one bridge to send and receive transactions between at least one input/output device and at least one processor; at least one crossbar coupled to at least one bridge to route transactions; and a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge. - View Dependent Claims (33, 34)
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35. Apparatus comprising:
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an interconnect to communicatively couple at least one processor with at least one input/output device, the interconnect including at least one bridge to send and receive transactions between at least one input/output device and at least one processor; at least one crossbar coupled to at least one bridge to route transactions; and at least one DMA engine coupled to the crossbar, the DMA engine to facilitate message-passing between at least one processor and at least one additional processor. - View Dependent Claims (36, 37, 38)
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Specification