Hysteresis in thermal throttling

• US 7,603,576 B2
• Filed: 06/21/2006
• Issued: 10/13/2009
• Est. Priority Date: 11/29/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Johns, Charles Ray, Wang, Michael Fan
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US11/425,499
• Publication Number:
  US 20070121699A1
• Time in Patent Office: 1,210 Days
• Field of Search: None
• US Class Current: 713/322
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/015 using microstructures, e.g. made of silicon
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer implemented method, data processing system, and processor are provided for hysteresis in thermal throttling. A digital thermal sensor senses a temperature in the integrated circuit. A determination is made as to whether the sensed temperature is greater than or equal to a throttling temperature. A throttling mode is initiated in response to the sensed temperature meeting or exceeding the throttling temperature. The digital thermal sensor senses a new temperature. A determination is made as to whether the new sensed temperature is less than an end throttling temperature. The throttling mode is disabled in response to the new sensed temperature being less than the end throttling temperature.

Claims

1. A computer implemented method for thermal throttling using hysteresis in a heterogeneous multi-core processor that is implemented on a single integrated circuit chip, comprising:

providing, in each one of a plurality of cores that are included in the heterogeneous multi-core processor, a separate digital thermal sensor that senses a temperature in the digital thermal sensor'"'"'s respective one of the plurality of cores;

setting, in a throttle point register that is included in the processor and outside of the plurality of cores, a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time;

sensing, by each digital thermal sensor, a temperature in each one of the plurality of cores;

determining if a first sensed temperature sensed by a first digital thermal sensor in a first one of the plurality of cores is greater than or equal to the first throttling temperature;

responsive to the first sensed temperature meeting or exceeding the first throttling temperature, initiating a throttling mode in only the first one of the plurality of cores;

sensing, by the first digital thermal sensor, a new first temperature;

determining if the new first temperature is less than an end throttling temperature; and

responsive to the new first temperature being less than the end throttling temperature, disabling the throttling mode in only the first one of the plurality of cores.

2. The method of claim 1, wherein the throttle point register is included in a thermal management control state machine residing within the processor and outside the plurality of cores.

3. The method of claim 1, wherein the first throttling temperature and the second throttling temperature are temperatures that are greater than the end throttling temperature.

4. The method of claim 1, wherein the throttling mode includes a type of throttling mode to be initiated.

5. The method of claim 4, wherein the type of throttling mode is at least one of dynamic throttling disabled, normal operation, power processor element or synergistic processor element is always throttled, core stop safety disabled, or power processor element or synergistic processor element is always throttled and core stop safety disabled.

6. The method of claim 1, wherein an external digital thermal sensor resides within the processor and outside of the plurality of cores.

7. The method of claim 1, wherein the throttling mode blocks a dispatch of instructions.

8. The method of claim 1, wherein the throttling mode slows down a clock frequency.

9. The method of claim 1, wherein the first and second throttling temperatures are programmable temperatures.

10. The method of claim 1, wherein the end throttling temperature is a programmable temperature.

11. The method of claim 1, further comprising:

setting, in each one of a plurality of control registers that are associated with a corresponding one of the plurality of cores, a separate specified throttling mode for a corresponding one of the plurality of cores, wherein the separate specified throttling mode is set for each one of the plurality of cores independently.

12. The method of claim 1, further comprising:

determining if a second sensed temperature sensed by a second digital thermal sensor in a second one of the plurality of cores is greater than or equal to the second throttling temperature;

responsive to the second sensed temperature meeting or exceeding the second throttling temperature, initiating a throttling mode in only the second one of the plurality of cores;

sensing, by the second digital thermal sensor, a new second temperature;

determining if the new second temperature is less than the end throttling temperature; and

responsive to the new second temperature being less than the end throttling temperature, disabling the throttling mode in only the second one of the plurality of cores.

13. The method of claim 1, further comprising:

further responsive to the first sensed temperature meeting or exceeding the first throttling temperature;

controlling the type of throttling of the first one of the plurality of processor cores as indicted by settings included in a control register in the processor;

controlling the amount of throttling of the first one of the plurality of processor cores as indicated by a stop time register that is included in the processor, wherein the stop time register specifies a number of clock cycles; and

controlling the duration of throttling of the first one of the plurality of processor cores as indicated by settings included in a scale register included in the processor,

wherein the scale register specifies a scale value; and

wherein when the first one of the plurality of processor cores is throttled, the first one of the plurality of processor cores is stopped for the number of clock cycles specified in the stop time register multiplied by the scale value specified by the scale register.

14. A data processing system comprising:

a bus;

a memory coupled to the bus, wherein the memory includes a set of instructions; and

a single integrated circuit chip on which is implemented a heterogeneous multi-core processor, wherein the processor is coupled to the bus, and wherein a separate digital thermal sensor is provided in each one of a plurality of cores that are included in the heterogeneous multi-core processor, wherein the separate digital thermal sensor senses a temperature in the digital thermal sensor'"'"'s respective one of the plurality of cores; and

further wherein the processor executes the set of instructions to;

set, in a throttle point register that is included in the processor and outside of the plurality of cores, a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time;

sense, by each digital thermal sensor, a temperature in each one of the plurality of cores;

determine if a first sensed temperature sensed by a first digital thermal sensor in a first one of the plurality of cores is greater than or equal to the first throttling temperature;

responsive to the first sensed temperature meeting or exceeding the first throttling temperature, initiate a throttling mode in only the first one of the plurality of cores;

sense, by the first digital thermal sensor, a new first temperature;

determine if the new first temperature is less than an end throttling temperature; and

responsive to the new first temperature being less than the end throttling temperature, disable the throttling mode in only the first one of the plurality of cores.

15. The system of claim 14, wherein the first throttling temperature and the second throttling temperatures are greater than the end throttling temperature.

16. The system of claim 14, wherein the throttling mode includes a type of throttling mode to be initiated.

17. The system of claim 14, wherein the throttling mode performs at least one of blocking a dispatch of instructions or slowing down a clock frequency.

18. The system of claim 14, wherein the integrated circuit further executes the set of instructions to set, in each one of a plurality of control registers that are included in the processor and outside of the plurality of cores, a separate specified throttling mode for a corresponding one of the plurality of cores, wherein the separate specified throttling mode is set independently for each one of the plurality of cores.

19. The system of claim 14, wherein the integrated circuit further executes the set of instructions to:

determine if a second sensed temperature sensed by a second digital thermal sensor in a second one of the plurality of cores is greater than or equal to the second throttling temperature;

responsive to the second sensed temperature meeting or exceeding the second throttling temperature, initiate a throttling mode in only the second one of the plurality of cores;

sense, by the second digital thermal sensor, a new second temperature;

determine if the new second temperature is less than the end throttling temperature; and

responsive to the new second temperature being less than the end throttling temperature, disable the throttling mode in only the second one of the plurality of cores.

20. The system of claim 14, wherein the integrated circuit further executes the set of instructions, further responsive to the first sensed temperature meeting or exceeding the first throttling temperature, to:

control the type of throttling of the first one of the plurality of processor cores as indicted by settings included in a control register in the processor;

control the amount of throttling of the first one of the plurality of processor cores as indicated by a stop time register that is included in the processor, wherein the stop time register specifies a number of clock cycles; and

control the duration of throttling of the first one of the plurality of processor cores as indicated by settings included in a scale register included in the processor, wherein the scale register specifies a scale value; and

wherein when the first one of the plurality of processor cores is throttled, the first one of the plurality of processor cores is stopped for the number of clock cycles specified in the stop time register multiplied by the scale value specified by the scale register.