Method and system for debugging a software program

• US 7,603,589 B2
• Filed: 05/15/2006
• Issued: 10/13/2009
• Est. Priority Date: 05/16/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Iqbal; Nadeem
• Application Number:
  US11/383,370
• Publication Number:
  US 20060259822A1
• Time in Patent Office: 1,247 Days
• Field of Search: 714 25- 27, 714 30- 33, 714 37- 39, 714/45, 714/46
• US Class Current: 714/45
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program

Abstract

A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target program (the processing circuit having a plurality of registers), a trace system operatively coupled to the processing circuit (the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program), a first memory operatively coupled to the processing circuit (the first memory comprising instructions to be executed by the processing circuit), and a memory location operatively coupled to the trace system (the memory location writable by the target program). The trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written.

Claims

1. An integrated circuit device comprising:

a processing circuit configured to execute a target program, the processing circuit having a plurality of registers;

a trace system operatively coupled to the processing circuit, the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program;

a first memory operatively coupled to the processing circuit, the first memory comprises a plurality of overlay regions;

a memory subsystem operatively coupled to the processing circuit, the memory subsystem comprises a plurality of overlay programs, wherein the processing circuit is configured to execute overlay programs from the plurality of overlay regions; and

a memory location operatively coupled to the trace system, the memory location writable by the target program;

wherein the trace system is configured to send a value stored in the memory location to a host computer only when the value is newly written, the value stored in the memory location is indicative of which of the plurality of overlay programs have been executed by the processing circuit.

2. The integrated circuit device as defined in claim 1 wherein the memory location further comprises a hardware register.

3. The integrated circuit device as defined in claim 2 wherein the hardware register is one selected from the group:

an instruction addressable register, or a memory mapped register.

4. The integrated circuit device as defined in claim 1 further comprising a log buffer configured to collect the trace data, wherein the trace system is configured to send entries from the log buffer to the debug program.

7. The integrated circuit device as defined in claim 1 further comprising a data flattener circuit operatively coupled to the processing circuit and the trace system, wherein the data flattener circuit is configured to serialize the trace data and send the serialized trace data to the trace system.

8. The integrated circuit device as defined in claim 7 further comprising an event trigger system operatively coupled to the data flattener circuit and the trace system, the event trigger system configured to receive a pre-programmed trigger, wherein the event trigger system is configured to assert a trigger signal to the trace system based on the pre-programmed trigger, and wherein the trace system is configured to collect the trace data based on the trigger signal.

5. An integrated circuit device comprising:

a processing circuit configured to execute a target program, the processing circuit having a plurality of registers;

a trace system operatively coupled to the processing circuit, the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program;

a first memory operatively coupled to the processing circuit, the first memory comprises a plurality of overlay regions;

a memory subsystem operatively coupled to the processing circuit, the memory subsystem comprises a plurality of overlay programs, wherein the processing circuit is configured to execute overlay programs from the plurality of overlay regions; and

a memory location operatively coupled to the trace system, the memory location writable by the target program;

wherein the trace system is configured to send a value stored in the memory location to a host computer only when the value is newly written, and the memory location is configured to be used as a bit map, wherein bits within the memory location are asserted to indicate which of the plurality of overlay programs have been loaded to the first memory.

6. An integrated circuit device comprising:

a processing circuit configured to execute a target program, the processing circuit having a plurality of registers;

a trace system operatively coupled to the processing circuit, the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program;

a first memory operatively coupled to the processing circuit, the first memory comprises a plurality of overlay regions;

a memory subsystem operatively coupled to the processing circuit, the memory subsystem comprises a plurality of overlay programs, wherein the processing circuit is configured to execute overlay programs from the plurality of overlay regions;

a log buffer writable by the target program and comprising values indicative of the identities of the plurality of overlay programs and index values corresponding to locations within the memory subsystem where the plurality of overlay programs are stored, and wherein a host computer reads the values from the log buffer; and

a memory location operatively coupled to the trace system, the memory location writable by the target program;

wherein the trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written.

9. An integrated circuit device comprising:

a processing circuit configured to execute a target program, the processing circuit having a plurality of registers comprising a program counter register that stores the address of the next instruction to be executed; and

a system operatively coupled to the processing circuit, the system configured to continually read a value from the program counter register and send an output to a host computer separate from the integrated circuit device at least one selected from the group consisting of;

the value; and

a preemptive value in place of the value upon notification of posting of a new preemptive value.

10. The integrated circuit device as defined in claim 9 wherein the system further comprises a multiplexer and a parallel to serial converter operatively coupled to the multiplexer, the multiplexer configured to receive a select signal, and the system configured to send the output of the parallel to serial converter to the host computer for use by a debug program.

11. The integrated circuit device as defined in claim 9 wherein a predetermined bit in a value of the program counter register is asserted to indicate the value is not the preemptive value.

12. The integrated circuit device as defined in claim 9 wherein the preemptive value is a value indicative of a non-viewable status of code within the target program.

13. The integrated circuit device as defined in claim 9 wherein a predetermined bit in the preemptive value is asserted to indicate the value is not a program counter value.

14. The integrated circuit device as defined in claim 9 further comprising a scan system configured to receive a signal from a control logic, wherein the scan system is further configured to receive an output signal from the system, and wherein the operation of the scan system is determined at least in part by the signal received from the control logic.

15. The integrated circuit device as defined in claim 10 wherein while the select signal is de-asserted, the output of the multiplexer is configured to provide a program counter value, wherein while the select signal is asserted, the output of the multiplexer is configured to provide one or more messages, one of which may be the program counter value, and wherein assertion and de-assertion of the select signal is configured to provide control of the output of the multiplexer based on a priority of the one or more messages.

16. A system comprising:

a host computer configured to execute a debug program; and

a target system electrically coupled to the host computer, wherein the target system comprises a processing circuit, a first memory operatively coupled to the processing circuit, a trace system operatively coupled to the processing circuit, and a memory location operatively coupled to the trace system;

wherein the processing circuit is configured to execute a target program and wherein the processing circuit comprises a plurality of registers;

wherein the first memory comprising instructions to be executed by the processing circuit;

wherein the trace system is configured to collect trace data comprising values of the plurality of registers, and wherein the trace system is configured to send the trace data to the host computer for use by the debug program;

wherein the memory location is writable by the target program; and

wherein the trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written, the value indicative of which of a plurality or overlay programs have been executed by the processing circuit.

17. The system as defined in claim 16 wherein the target system is electrically coupled to the host computer by way of a connection selected from the group:

a multi-pin connection, a serial connection, or an optical interconnection.