Stacked integrated circuit assembly

• US 7,605,477 B2
• Filed: 01/25/2007
• Issued: 10/20/2009
• Est. Priority Date: 01/25/2007
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Dearden, Timothy E., Quan, Clifton, Chan, Polwin C., Hauhe, Mark S., Wong, Tse E., Tonomura, Samuel D., Sox, Stephen E.
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US11/698,602
• Publication Number:
  US 20080179758A1
• Time in Patent Office: 999 Days
• Field of Search: 257/777, 257/686, 257/778, 257/E23.021
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Claims

1. A stacked integrated circuit assembly, comprising:

a substrate having a top surface with at least one substrate connection pad;

a first flip chip integrated circuit (FFIC) disposed above the substrate;

a second flip chip integrated circuit (SFIC) disposed above the FFIC, the FFIC disposed between the substrate and the SFIC;

a first solder connection between the substrate connection pad and the FFIC; and

a second solder connection between the FFIC and the SFIC,

wherein a first melting temperature of the first solder connection is different than a second melting temperature of the second solder connection and wherein connection pads of the FFIC, the SFIC and the substrate are coplanar with respective surfaces of the FFIC, the SFIC and the substrate, the respective surfaces each face corresponding solder connections.

2. The assembly of claim 1, wherein the FFIC comprises a die having a first semiconductor material, and the SFIC comprises a die having a second semiconductor material, the second semiconductor material differing from the first semiconductor material.

3. The assembly of claim 1, wherein the assembly is operable to process microwave frequency electrical signals.

4. A stacked integrated circuit assembly, comprising:

a substrate having a top surface, and at least one substrate connection pad disposed upon the top surface;

a first flip chip integrated circuit (FFIC), the FFIC comprising;

a FFIC front surface and opposite thereto a FFIC back surface, the FFIC front surface proximate to the substrate top surface;

at least one FFIC front connection pad disposed upon the FFIC front surface, each FFIC front connection pad aligned to at least one substrate connection pad;

at least one electrically conductive through die via, each through die via electrically coupled to one FFIC front connection pad and extending from the FFIC front surface to the FFIC back surface;

at least one FFIC back connection pad disposed upon the FFIC back surface, each FFIC back connection pad electrically coupled to one through die via; and

a die having a first semiconductor material;

a second flip chip integrated circuit (SFIC), the SFIC including;

a SFIC front surface and opposite thereto a SFIC back surface, the SFIC front surface proximate to the FFIC back surface;

at least one SFIC front connection pad disposed upon the SFIC front surface, each SFIC front connection pad aligned to at least one FFIC back connection pad; and

a die having a second semiconductor material, the second semiconductor material differing from the first semiconductor material;

a first solder connection between each FFIC front connection pad and each substrate connection pad, the first solder connection establishing a first gap between the FFIC front surface and the substrate; and

a second solder connection between each SFIC front connection pad and each FFIC back connection pad, the second solder connection establishing a second gap between the SFIC front surface and the FFIC back surface; and

wherein the assembly is operable to process microwave frequency electrical signals

wherein a first melting temperature of the first solder connection is lower than a second melting temperature of the second solder connection and wherein the connection pads of the FFIC, the SFIC and the substrate are coplanar with the front and the back surfaces of the FFIC, the front surface of the SFIC and the top surface of the substrate respectively.

5. The assembly of claim 4, wherein the first semiconductor material comprises silicon and germanium, and the second semiconductor material comprises gallium and arsenic.

6. The assembly of claim 4, wherein the FFIC and the SFIC comprise monolithic microwave integrated circuits.

7. The assembly of claim 4, wherein the substrate comprises a printed circuit board.

8. The assembly of claim 4, wherein each through die via is plated with an electrically conductive material.

9. The assembly of claim 4, wherein each through die via is filled with an electrically conductive material.

10. The assembly of claim 4, wherein each FFIC front connection pad is positioned adjacent to the through die via that the FFIC front connection pad is electrically coupled to.

11. The assembly of claim 4, wherein each FFIC back connection pad is positioned adjacent to the through die via that the FFIC back connection pad is electrically coupled to.

12. The assembly of claim 4 further comprising a first underfill material positioned in the first gap.

13. The assembly of claim 4 further comprising a second underfill material positioned in a subset of the second gap.

14. The assembly of claim 4, wherein the FFIC is positioned about parallel to the SFIC.

15. The assembly of claim 4, wherein the FFIC is positioned about parallel to the substrate.

16. The assembly of claim 4, wherein a first thickness of the first gap is about equal to a second thickness of the second gap.