Deep under voltage recovery in a battery pack

• US 7,605,568 B2
• Filed: 03/10/2006
• Issued: 10/20/2009
• Est. Priority Date: 03/10/2006
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated), Sony Corporation (Sony Group Corp.)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated), Sony Corporation (Sony Group Corp.)
• Inventors: Kastnes, Paal Ronny, Gangstoe, Gunnar, Sato, Hideyuki, Aas, Arne
• Primary Examiner(s): Ullah; Akm E
• Assistant Examiner(s): DIAO, M BAYE
• Application Number:
  US11/373,843
• Publication Number:
  US 20070210757A1
• Time in Patent Office: 1,320 Days
• Field of Search: 320/106, 320/120, 320/121, 320/122, 320/124, 320/125, 320/128, 320/129, 320/132, 320/134, 320/135, 320/136, 320/164, 320/165, 320/137
• US Class Current: 320/137
• CPC Class Codes: H02J 7/0029 with safety or protection devices or circuits
• CPC Class Codes: H02J 7/0036 using connection detecting circuits H02J7/0034 takes precedence
• CPC Class Codes: H02J 7/0069 Charging or discharging for charge maintenance, battery initiation or rejuvenation

Abstract

In one implementation, a method for charging a battery system is provided. The method includes enabling determining if a charger is coupled to a battery system, the battery system including one or more cells and a charge enable transistor. The method also includes enabling determining if a voltage level of the cells is less than a predetermined first low voltage level. If the voltage level of the cells is less than the predetermined first low voltage level, enabling charging of the cells at a reduced rate including adjusting a voltage applied to the charge transistor gate terminal to regulate a voltage seen by the charger to a level that is less than a predetermined second voltage level. Additionally, when the voltage of the cells reaches the predetermined first low voltage level, the method includes substantially fully enabling the charge transistor to allow for charging at full rate by the charger.

Claims

1. A method for charging a battery system comprising:

determining that a charger is coupled to a battery system, the battery system including one or more cells and a charge transistor, where;

the battery system is distinct from the charger,

the charger monitors a voltage level of the battery system, and

the charger is operable to charge in two or more modes of operation and switch between the two or more modes of operation based on the voltage level of the battery system monitored by the charger;

determining that a voltage level of the cells is less than a first low voltage level,where the voltage level of the cells is distinct from the voltage level of the battery system monitored by the charger;

charging the cells at a reduced rate including adjusting a voltage applied to a charge transistor gate terminal, including;

regulating the voltage level of the battery system monitored by the charger to a level that is less than a second voltage level, where the charger does not switch between the two or more modes of operation, and

supplying a minimum operating voltage for at least one component of the battery system; and

when the voltage of the cells reaches the first low voltage level, substantially fully enabling the charge transistor to allow the charger to switch between the two or more modes of operation.

2. The method of claim 1 where adjusting a voltage applied to the gate terminal of the charge transistor includes partially enabling the charge transistor.

3. The method of claim 2 where partially enabling the charge transistor includes partially enabling the charge transistor until a voltage of the cells exceeds the first low voltage level.

4. The method of claim 2 where partially enabling the charge transistor includes adjusting a potential across the charge transistor to be higher than a difference between a potential of the cells and the minimum operating voltage.

5. The method of claim 2 where:

the two or more modes of operation include a reduced charge rate mode of charging and a normal charge rate mode of charging;

the charger switches to the reduced charge rate mode of charging when the voltage level of the battery system monitored by the charger is less than the first low voltage level; and

the charger switches to the normal charge rate mode of charging when the voltage level of the battery system monitored by the charger reaches the first low voltage level.

6. The method of claim 1 where the battery system includes a battery management system including battery monitoring circuitry and where adjusting a voltage applied to the charge transistor includes adjusting a drive signal to the charge transistor to maintain a voltage seen at an input to the battery management system at a level higher than a minimum operating voltage for the battery management system.

7. The method of claim 1 where the battery system includes a battery management system including battery monitoring circuitry and where adjusting a voltage applied to the charge transistor includes adjusting a drive signal to the charge transistor to maintain a voltage seen at an input to the battery management system at a level that is lower than a voltage level where the charger will switch from a reduced charge rate to a normal charge rate.

8. The method of claim 1 further comprising:

prior to charging the cells at a reduced rate, enabling monitoring circuitry in the battery system; and

monitoring the reduced rate charging of the cells.

9. The method of claim 8 further comprising safety monitoring the battery system while charging.

10. The method of claim 8 further comprising monitoring a change in a capacity of the cells of the battery system while charging.

11. The method of claim 1 where adjusting a voltage applied to the charge transistor includes determining if an operating voltage of the battery system is above a predefined maximum, and if so, increasing a drive voltage presented to the charge transistor.

12. The method of claim 1 where adjusting a voltage applied to the charge transistor includes determining if an operating voltage of the battery system is below a predefined minimum, and if so, decreasing a drive voltage presented to the charge transistor.

13. The method of claim 1 further including:

enabling the charge monitor control circuitry included in the battery system prior to charging the cells.

14. The method of claim 1 further comprising:

monitoring, using monitoring circuitry of the battery system, the one or more cells voltage level and determining if the monitored voltage level is below the first threshold voltage level.

15. An apparatus comprising:

a high-side NFET charge transistor;

a drive circuit for driving the high-side NFET charge transistor; and

a monitor circuit coupled to the drive circuit for monitoring a voltage level of a battery cell to be charged;

where, when a charger distinct from the apparatus is coupled to the apparatus, the drive circuit is operable to perform operations comprising;

partially enabling the high-side NFET charge transistor if the voltage level of the battery cell is below a first threshold level including supplying a minimum operating voltage of the monitor circuit, where the charger does not switch between two or more modes of operation, and

substantially fully enabling the charge transistor when the voltage level of the battery cell reaches the first threshold level to allow the charger to switch between the two or more modes of operation.

16. The apparatus of claim 15 where:

partially enabling the high-side NFET charge transistor further includes regulating a voltage level of the apparatus monitored by the charger to a level that is less than a second voltage level.

17. The apparatus of claim 16 where:

the drive circuit includes a recovery circuit operable to control partially enabling the high-side NFET charge transistor, the recovery circuit including;

a combinational logic circuit;

a plurality of comparators coupled to the combinational logic circuit; and

a switch coupled to the plurality of comparators and operable to partially enable the high-side NFET charge transistor based on a signal from the plurality of comparators.