Intra-chip power and test signal generation for use with test structures on wafers

• US 7,605,597 B2
• Filed: 11/05/2007
• Issued: 10/20/2009
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tel Venture Capital, Inc. (Tokyo Electron Limited)
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Vickers, James S., Estabil, Jose J.
• Primary Examiner(s): Karlsen; Ernest F
• Application Number:
  US11/935,297
• Publication Number:
  US 20080100319A1
• Time in Patent Office: 715 Days
• Field of Search: 324/763, 324/765, 257/48, 438 11- 18, 700/121, 714/733, 714/734
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. An arrangement for evaluating a fabrication of at least a partially-fabricated wafer, wherein the arrangement comprises:

a circuit element provided within an active region of a die of the wafer;

a power receiver provided in the active region of the die and connected to the circuit element, wherein the power receiver is configured to generate a power signal for the circuit element in response to receiving a power input;

a test/trigger receiver provided in the active region of the die and connected to the circuit element, wherein the test/trigger receiver is configured to generate a trigger signal for the circuit element in response to receiving a signal input;

wherein in response to receiving the power signal and the trigger signal, the circuit element is configured to exhibit an electrical activity that is detectable by a test probe without affecting a usability of a chip that is formed from the die, and wherein the electrical activity is indicative of one or more characteristics that are a result of the fabrication.

2. The arrangement of claim 1, wherein the test/trigger receiver is configured to generate the trigger signal for the circuit element in response to receiving an energy beam.

3. The arrangement of claim 1, wherein the test/trigger receiver is configured to generate the trigger signal for the circuit element in response to receiving a modulating energy beam.

4. The arrangement of claim 1, wherein the power receiver is configured to generate a power signal for the circuit element in response to receiving an energy beam.

5. The arrangement of claim 1, wherein the power receiver is configured to receive the power input without contacting a source of the power input.

6. The arrangement of claim 1, wherein the power receiver includes a voltage step-up to increase a voltage of the power signal before it is supplied to the circuit element.

7. The arrangement of claim 1, wherein the power receiver includes a photodiode.

8. The arrangement of claim 1, wherein:

the power receiver is configured to generate a power signal for the circuit element in response to receiving a constant laser beam;

the test/trigger receiver is configured to generate the trigger signal for the circuit element in response to receiving a modulating laser beam.

9. The arrangement of claim 1, wherein the circuit element is configured to exhibit the electrical activity corresponding to a detectable production of photons.

10. The arrangement of claim 1, wherein the circuit element is configured to exhibit the electrical activity corresponding to an output signal from the circuit element.