Programmable level shifter

• US 7,605,609 B1
• Filed: 12/17/2007
• Issued: 10/20/2009
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Andrews, William B., Schadt, John, Lin, Mou C.
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): LO, CHRISTOPHER KWOK YEUNG
• Application Number:
  US11/957,598
• Time in Patent Office: 673 Days
• Field of Search: 326 62- 63, 326/68, 326 80- 83, 326 86- 87, 327/333
• US Class Current: 326/68
• CPC Class Codes: H03K 3/356165 using additional transistors in the feedback circuit

Abstract

In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

Claims

1. An integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain, wherein:

switching speed of the level shifter is higher in the high-speed mode than in the low-power mode;

power consumption of the level shifter is lower in the low-power mode than in the high-speed mode; and

the programmable level shifter comprises;

first and second devices that are configured as a current-mirror amplifier in the high-speed mode and as a cross-coupled latch in the low-power mode;

first, second, third, and fourth n-type devices, wherein;

the first and third n-type devices are connected in parallel;

the second and fourth n-type devices are connected in parallel;

in the high-speed mode, the third and fourth n-type devices are disabled; and

in the low-power mode, the third and fourth n-type devices are enabled, such that (1) the first and third n-type devices form a first relatively large effective n-type device and (2) the second and fourth n-type devices form a second relatively large effective n-type device.

2. The invention of claim 1, wherein one or more transistors in the programmable level shifter are shared by the high-speed mode and the low-power mode.

3. The invention of claim 1, wherein the first and second devices are p-type devices.

4. The invention of claim 3, wherein the programmable level shifter further comprises third and fourth p-type devices that are controlled by a mode-control signal to configure the first and second p-type devices (1) as the current-mirror amplifier for the high-speed mode and (2) as the cross-coupled latch for the low-power mode.

5. The invention of claim 1, wherein the programmable level shifter further comprises first and second muxes that are controlled by a mode-control signal to (1) disable the third and fourth n-type devices for the high-speed mode and (2) enable the third and fourth n-type devices for the low-power mode.

6. The invention of claim 1, wherein the integrated circuit is an FPGA.

7. An integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain, wherein:

switching speed of the level shifter is higher in the high-speed mode than in the low-power mode;

power consumption of the level shifter is lower in the low-power mode than in the high-speed mode; and

the programmable level shifter comprises;

first and second p-type devices that are configured as a current-mirror amplifier in the high-speed mode and as a cross-coupled latch in the low-power mode;

third and fourth p-type devices that are controlled by a mode-control signal to configure the first and second p-type devices (1) as the current-mirror amplifier for the high-speed mode and (2) as the cross-coupled latch for the low-power mode;

first, second, third, and fourth n-type devices, wherein the first and third n-type devices are connected in parallel;

the second and fourth n-type devices are connected in parallel;

in the high-speed mode, the third and fourth n-type devices are disabled; and

in the low-power mode, the third and fourth n-type devices are enabled, such that (1) the first and third n-type devices form a first relatively large effective n-type device and (2) the second and fourth n-type devices form a second relatively large effective n-type device; and

first and second muxes that are controlled by the mode-control signal to (1) disable the third and fourth n-type devices for the high-speed mode and (2) enable the third and fourth n-type devices for the low-power mode.

8. The invention of claim 7, wherein the first and second p-type devices and the first and second n-type devices are shared by the high-speed mode and the low-power mode.

9. The invention of claim 7, wherein the integrated circuit is an FPGA.

10. An integrated circuit comprising:

first means for converting, in a high-speed mode, an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain; and

second means for converting, in a low-power mode, the input signal in the first power supply domain into the output signal in the second power supply domain, wherein;

switching speed of the first means is higher than switching speed of the second means;

power consumption of the first means is lower than power consumption of the second means;

the first and second means share first and second devices that are configured as a current-mirror amplifier in the first means and as a cross-coupled latch in the second means,

wherein;

the second means further comprises first, second, third, and fourth n-type devices;

the first and third n-type devices are connected in parallel in the second means to form a first relatively large effective n-type device;

the second and fourth n-type devices are connected in parallel in the second means to form a second relatively large effective n-type device; and

the first and second means share the first and third n-type devices, but not the second and fourth n-type devices.

11. The invention of claim 10, wherein the first and second devices are p-type devices.

12. The invention of claim 11, wherein the integrated circuit further comprises third and fourth p-type devices that are controlled by a mode-control signal to configure the first and second p-type devices (1) as the current-mirror amplifier in the first means and (2) as the cross-coupled latch in the second means.

13. The invention of claim 10, wherein the integrated circuit further comprises first and second muxes that are controlled by a mode-control signal to (1) exclude the third and fourth n-type devices from the first means and (2) include the third and fourth n-type devices in the second means.

14. An integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain, wherein:

switching speed of the level shifter is higher in the high-speed mode than in the low-power mode;

power consumption of the level shifter is lower in the low-power mode than in the high-speed mode;

the programmable level shifter comprises first, second, third, and fourth devices, wherein;

the first and third devices are connected in parallel;

the second and fourth devices are connected in parallel;

in the high-speed mode, the third and fourth devices are disabled; and

in the low-power mode, the third and fourth devices are enabled, such that (1) the first and third devices form a first relatively large effective device and (2) the second and fourth devices form a second relatively large effective device; and

the programmable level shifter further comprises first and second muxes that are controlled by a mode-control signal to (1) disable the third and fourth devices for the high-speed mode and (2) enable the third and fourth devices for the low-power mode.

15. The invention of claim 14, wherein the first, second, third, and fourth devices are n-type devices.

16. The invention of claim 14, wherein the integrated circuit is an FPGA.