Differential current driving type transmission system

• US 7,605,610 B2
• Filed: 04/25/2006
• Issued: 10/20/2009
• Est. Priority Date: 04/26/2005
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Jong-Kee, Oh, Woon-Taek, Sung, Yoo-Chang
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): LO, CHRISTOPHER KWOK YEUNG
• Application Number:
  US11/411,571
• Publication Number:
  US 20060238037A1
• Time in Patent Office: 1,274 Days
• Field of Search: 326/21, 326 30- 31, 326 82- 83, 326 86- 87, 326/68, 326/112, 326/115, 326/121, 326/127, 326/26, 326/34, 327/108, 327/109, 327/53, 327/132, 375219-220
• US Class Current: 326/86
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

There is provided a differential current driving current type transmission system. The system includes a transmission line pair for transmitting a signal by a differential scheme; a transmission unit having a transmission circuit for making the transmission line pair have a current difference according to a logic value of a transmission signal and equalizing the transmission line pair at a predetermined timing, and a transmission controller for controlling the signal transmission of the transmission circuit and the equalization of the transmission line pair; and a receiving unit having an I-V converter circuit for mirroring a current difference of the transmission line pair and converting the current difference into a voltage difference, and a differential amplifier for amplifying the voltage difference of the I-V converter circuit.

Claims

1. A transmitter for use in a differential current driving type system, comprising:

a current source means for supplying different current amount to a first and a second lines of a transmission line pair in response to a logic value of data transmitted through the first and the second lines; and

a transmission controller for controlling the current source means,

wherein the current source means includes an equalizing switch for connecting the first line with the second line to equalize a first potential level of the first line and a second potential level of the second line

wherein the transmission controller controls the equalizing switch to be turned off for a predetermined time when the data to be transmitted in a current data period is different from a previous data bit transmitted in a previous data period, to be turned on after the predetermined time, and to maintain turn-on during a time period that the logic value of the data to be transmitted is not changed.

2. The transmitter as recited in claim 1, wherein the current source means further includes:

a first current source for supplying a first current to the first line;

a second current source for supplying a second current to the second line;

a transition current source for generating a transmission current indicating a logic state transition to one of the transmission line pair; and

a transition switch for supplying the transition current to one of the transmission line pair according to the logic value of the data.

3. The transmitter as recited in claim 1, wherein the predetermined time is a PT/2 and the data period is a PT.

4. The transmitter as recited in claim 3, wherein the equalizing switch is turned off for PT/2 from a different data is inputted from a previous data bit.

5. The transmitter as recited in claim 2, further comprising a reference mirror MOS transistor of which a drain and a gate are connected to each other, enabling a reference current to pass therethrough, wherein the reference current is a basis for generating the base current and the transition current.

6. The transmitter as recited in claim 5, wherein the first current source is a first base mirror MOS transistor of which a source and a drain are connected to a power supply voltage and the true line, respectively, and a gate is connected to a gate of the reference mirror MOS transistor, and the second current source is a second base mirror MOS transistor of which a source and a drain are connected to the power supply voltage and the bar line, respectively, and a gate is connected to the gate of the reference mirror MOS transistor.

7. The transmitter as recited in claim 5, wherein the transition current source is a transition mirror MOS transistor of which a source and a drain are connected to the power supply voltage and the transition switch, respectively, and a gate is connected to the gate of the reference mirror MOS transistor.

8. The transmitter as recited in claim 2, wherein the transition switch comprises:

a first transition switch configured with a 2-MOS switch, receiving a transition signal and an inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the true line; and

a second transition switch configured with a 2-MOS switch, receiving a transition signal and an inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the bar line.

9. The transmitter as recited in claim 2, wherein the transition switch comprises:

a first transition switch configured with a single MOS switch, receiving a transition signal or an inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the true line; and

a second transition switch configured with a single MOS switch, receiving a transition signal or inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the bar line.

10. The transmitter as recited in claim 2, wherein the equalizing switch is configured with a 2 MOS switch, receiving an equalizing signal and an inversion equalizing signal through a gate thereof, of which one end is connected to the true line and the other end is connected to the bar line.

11. The transmitter as recited in claim 2, wherein the equalizing switch is configured with a single MOS switch, receiving an equalizing signal or an inversion equalizing signal through a gate thereof, of which one end is connected to the true line and the other end is connected to the bar line.

12. A differential current driving type transmission system, comprising:

a transmission line pair for transmitting a signal by a differential scheme;

a transmission unit including a transmission circuit for making the transmission line pair have a current difference according to a logic value of a transmission signal and equalizing the transmission line pair at a predetermined timing, and a transmission controller for controlling the signal transmission of the transmission circuit and the equalization of the transmission line pair; and

a receiving unit including an I-V converter circuit for mirroring a current difference of the transmission line pair and converting the current difference into a voltage difference, and a differential amplifier for amplifying the voltage difference of the I-V converter circuit,

wherein the transmission circuit includes an equalizing switch for connecting the transmission line pair to each other to equalize a first potential level of a true line and a second potential level of a bar line

wherein the transmission controller controls the equalizing switch to be turned off for a predetermined time when the data to be transmitted in a current data period is different from a previous data bit transmitted in a previous data period, to be turned on after the predetermined time, and to maintain turn-on during a time period that the logic value of the data to be transmitted is not changed.

13. The differential current driving type transmission system as recited in claim 12, wherein the transmission circuit further comprises:

a first current source for supplying a base current indicating a base logic state to the true line of the transmission line pair;

a second current source for supplying a base current indicating a base logic state to the bar line of the transmission line pair;

a transition current source for generating a transmission current indicating a transmission logic state to one of the transmission line pair; and

a transition switch for supplying the transition current to the true line or the bar line according to a logic value of the data to be transmitted.

14. The differential current driving type transmission system as recited in claim 12, wherein the predetermined time is a PT/2.

15. The differential current driving type transmission system as recited in claim 14, wherein the equalizing switch is turned off for PT/2 from a different data is inputted from a previous data bit.

16. The differential current driving type transmission system as recited in claim 13, further comprising a reference mirror MOS transistor of which a drain and a gate are connected to each other, enabling a reference current to pass therethrough, wherein the reference current is a basis for generating the base current and the transition current.

17. The differential current driving type transmission system as recited in claim 16, wherein the first current source is a first base mirror MOS transistor of which a source and a drain are connected to a power supply voltage and the true line, respectively, and a gate is connected to a gate of the reference mirror MOS transistor, and the second current source is a second base mirror MOS transistor of which a source and a drain are connected to the power supply voltage and the bar line, respectively, and a gate is connected to the gate of the reference mirror MOS transistor.

18. The differential current driving type transmission system as recited in claim 16, wherein the transition current source is a transition mirror MOS transistor of which a source and a drain are connected to the power supply voltage and the transition switch, respectively, and a gate is connected to the gate of the reference mirror MOS transistor.

19. The differential current driving type transmission system as recited in claim 13, wherein the transition switch comprises:

a first transition switch configured with a 2-MOS switch, receiving a transition signal and an inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the true line; and

a second transition switch configured with a 2-MOS switch, receiving a transition signal and an inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the bar line.

20. The differential current driving type transmission system as recited in claim 13, wherein the transition switch comprises:

a first transition switch configured with a single MOS switch, receiving a transition signal or an inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the true line; and

a second transition switch configured with a single MOS switch, receiving a transition signal or inversion transition signal through a gate thereof, of which one end is connected to the transition current source and the other end is connected to the bar line.

21. The differential current driving type transmission system as recited in claim 13, wherein the equalizing switch is configured with a 2 MOS switch, receiving an equalizing signal and an inversion equalizing signal through a gate thereof, of which one end is connected to the true line and the other end is connected to the bar line.

22. The differential current driving type transmission system as recited in claim 13, wherein the equalizing switch is configured with a single MOS switch, receiving an equalizing signal or an inversion equalizing signal through a gate thereof, of which one end is connected to the true line and the other end is connected to the bar line.

23. The differential current driving type transmission system as recited in claim 13, wherein the I-V converting circuit comprises:

a true line current mirror for generating a true line mirroring current by mirroring a data signal current flowing through a true line of a transmission line pair;

a bar line current mirror for generating a bar line mirroring current by mirroring a data signal current flowing through a bar line of the transmission line pair;

a true line I-V converter for generating a true line receiving voltage having a level corresponding to the true line mirroring current; and

a bar line I-V converter for generating a bar line receiving voltage having a level corresponding to the bar line mirroring current.

24. The differential current driving type transmission system as recited in claim 23, wherein the true line current mirror and the bar line current mirror generate the mirroring currents which are two times or greater than the current to be mirrored.

25. The differential current driving type receiver as recited in claim 23, wherein each of the true line current mirror and the bar line current mirror comprises:

an input terminal MOS transistor for making the current to be mirrored flow therethrough; and

an output terminal MOS transistor for making the mirroring current flow therethrough, wherein an input terminal of the current to be mirrored is connected to a gate of each of the input and output terminal MOS transistors.

26. The differential current driving type transmission system as recited in claim 23, wherein the true line I-V converter disposed on a current path of the true line mirroring current, comprises a first resistor of which one end is connected to a power supply voltage and the other end is connected to an output terminal of a true line conversion voltage, and the bar line I-V converter disposed on a current path of the bar line mirroring current, comprises a second resistor of which one end is connected to the power supply voltage and the other end is connected to an output terminal of a bar line conversion voltage.

27. The differential current driving type transmission system as recited in claim 23, wherein the true line I-V converter disposed on the current path of the true line mirroring current, further comprises a third resistor of which one end is connected to the output terminal of the true line conversion voltage and the other end is connected to the true line current mirror, and the bar line I-V converter disposed on the current path of the bar line mirroring current, further comprises a fourth resistor of which one end is connected to the output terminal of the bar line conversion voltage and the other end is connected to the bar line mirror.

28. The differential current driving type transmission system as recited in claim 23, wherein the first resistor is configured with a first resistor MOS transistor receiving a bias voltage through a gate thereof, of which a source and a drain are connected to the power supply voltage and the output terminal of the true line conversion voltage, respectively, and the second resistor is configured with a second resistor MOS transistor receiving a bias voltage through a gate thereof, of which a source and a drain are connected to the power supply voltage and the output terminal of the bar line conversion voltage, respectively.

29. The differential current driving type transmission system as recited in claim 27, wherein the third resistor is configured with a third resistor MOS transistor receiving a bias voltage through a gate thereof, of which a source and a drain are connected to the true line current mirror and the output terminal of the true line conversion voltage, respectively, and the fourth resistor is configured with a fourth resistor MOS transistor receiving a bias voltage through a gate thereof, of which a source and a drain are connected to the bar line current mirror and the output terminal of the bar line conversion voltage, respectively.

30. The differential current driving type transmission system as recited in claim 27, wherein the third resistor is configured with a third resistor MOS transistor of which a source is connected to the true line current mirror, and a drain and a gate are connected to the output terminal of the true line conversion voltage, and the fourth resistor is configured with a fourth resistor MOS transistor of which a source is connected to the bar line current mirror, and a drain and a gate are connected to the output terminal of the bar line conversion voltage.