Delay line synchronizer apparatus and method

• US 7,605,631 B2
• Filed: 11/14/2005
• Issued: 10/20/2009
• Est. Priority Date: 04/05/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Almo; Khareem E.
• Application Number:
  US11/274,857
• Publication Number:
  US 20060066375A1
• Time in Patent Office: 1,436 Days
• Field of Search: None
• US Class Current: 327/291
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

Claims

1. A method for adjusting a delay of an adjustable delay, comprising:

decoupling an input of the adjustable delay from receiving an input clock signal;

decoupling an output of the adjustable delay from providing an output clock signal;

after decoupling the adjustable delay, adjusting the delay from a current delay to a new delay;

recoupling the output of the adjustable delay;

recoupling the input of the adjustable delay to receive the input clock signal; and

while the input of the adjustable delay is decoupled, tracking an edge relationship of a reference clock signal and the input clock signal having a different clock frequency than the reference clock signal, the input clock signal provided to the adjustable delay and maintaining the edge relationship after recoupling the input and output of the adjustable delay.

2. The method of claim 1 wherein the frequency of the input clock signal is an even multiple of the frequency of the reference clock signal.

3. The method of claim 1 wherein the edge relationship of the reference and input clock signals comprises a rising edge of the input clock signal relative to a rising edge of the reference clock signal.

4. The method of claim 1 wherein the input of the adjustable delay is decoupled before the output of the adjustable delay is decoupled.

5. The method of claim 1 wherein the output of the adjustable delay is recoupled before the input of the adjustable delay is recoupled.

6. The method of claim 1, further comprising coupling the input and output to ground after the input and output are decoupled.

7. The method of claim 1 wherein decoupling an input of the adjustable delay and decoupling an output of the adjustable delay comprises:

latching a trigger signal in response to reference clock signal;

propagating the trigger signal through a first plurality of shift register stages in response to the input clock signal to provide a first control signal, the input clock signal having a clock frequency greater than the reference clock signal;

propagating the trigger signal through at least one additional shift register stage in response to the input clock signal to provide a second control signal; and

decoupling the input in response to the first control signal and decoupling the output in response to the second control signal.

8. A method for generating a clock signal, comprising:

receiving a clock signal in a first clock domain;

generating a clock signal in a second clock domain having a phase relationship relative to a clock edge of the clock signal in the first clock domain, the clock signal in the second clock domain having a higher frequency than the clock signal in the first clock domain;

ceasing generation of the clock signal in the second clock domain;

adjusting the phase relationship between the clock signals in the first and second clock domains to a new phase relationship while generation of the clock signal in the second clock domain is ceased; and

generating the clock signal in the second clock domain having the new phase relationship relative to the clock edge of the clock signal in the first clock domain.

9. The method of claim 8, further comprising:

monitoring the clock edge of the clock signal in the first clock domain to which the phase relationship is relative.

10. The method of claim 8 wherein generating the clock signal in the second clock domain comprises providing an input clock signal to an input of an adjustable delay circuit delaying the input clock signal by a delay to provide at an output the clock signal in the second clock domain.

11. The method of claim 10 wherein ceasing generation of the clock signal in the second clock domain comprises:

decoupling the input clock signal from the input of the adjustable delay circuit; and

decoupling the output from providing the clock signal in the second clock domain.

12. The method of claim 11 wherein the input clock signal is decoupled from the input before the output is decoupled.

13. The method of claim 11 wherein generating the clock signal in the second clock domain comprises:

recoupling the output to provide the clock signal in the second clock domain;

recoupling the input clock signal to the input of the adjustable delay circuit.

14. The method of claim 13 wherein the output is recoupled before the input clock signal is recoupled to the input of the adjustable delay circuit.

15. The method of claim 8 wherein generating a clock signal in the second clock domain comprises generating a clock signal having a frequency greater than the clock signal in the first clock domain and having a phase relationship relative to a rising edge of the clock signal in the first clock domain.

16. A method of operating a memory device, comprising:

latching data in response to a delayed clock signal, the delayed clock signal provided by an adjustable delay;

adjusting a delay of the adjustable delay, comprising;

decoupling an input of the adjustable delay from receiving an input clock signal;

after decoupling the adjustable delay, decoupling an output of the adjustable delay from providing an output clock signal;

adjusting the delay from a current delay to a new delay;

recoupling the output of the adjustable delay;

recoupling the input of the adjustable delay to receive the input clock signal;

while the input of the adjustable delay is decoupled, tracking an edge relationship of a reference clock signal and the input clock signal having a different clock frequency than the reference clock signal, the input clock signal provided to the adjustable delay and maintaining the edge relationship after recoupling the input and output of the adjustable delay; and

latching data in response to the delayed clock signal having the new delay.

17. The method of claim 16 wherein the edge relationship of the reference and input clock signals comprises a rising edge of the input clock signal relative to a rising edge of the reference clock signal.

18. The method of claim 16 wherein the input of the adjustable delay is decoupled before the output of the adjustable delay is decoupled.

19. The method of claim 16 wherein the output of the adjustable delay is recoupled before the input of the adjustable delay is recoupled.

20. The method of claim 16 wherein decoupling an input of the adjustable delay and decoupling an output of the adjustable delay comprises:

latching a trigger signal in response to the reference clock signal;

propagating the trigger signal through a first plurality of shift register stages in response to the input clock signal to provide a first control signal, the input clock signal having a clock frequency greater than the reference clock signal;

propagating the trigger signal through at least one additional shift register stage in response to the input clock signal to provide a second control signal; and

decoupling the input in response to the first control signal and decoupling the output in response to the second control signal.

21. A method of operating a memory device, comprising:

receiving a clock signal in a first clock domain;

generating an internal clock signal in a second clock domain having a phase relationship relative to a clock edge of the clock signal in the first clock domain, the clock signal in the second clock domain having a higher frequency than the clock signal in the first clock domain;

ceasing generation of the internal clock signal;

adjusting the phase relationship between the clock signals in the first clock domain and the internal clock signal to a new phase relationship while generation of the clock signal in the second clock domain is ceased;

generating the internal clock signal having the new phase relationship relative to the clock edge of the clock signal in the first clock domain; and

latching data in response to the internal clock signal.

22. The method of claim 21, further comprising:

monitoring the clock edge of the clock signal in the first clock domain to which the phase relationship is relative.

23. The method of claim 21 wherein generating the clock signal in the second clock domain comprises providing an input clock signal to an input of an adjustable delay circuit delaying the input clock signal by a delay to provide at an output the clock signal in the second clock domain.

24. The method of claim 23 wherein ceasing generation of the clock signal in the second clock domain comprises:

decoupling the input clock signal from the input of the adjustable delay circuit; and

decoupling the output from providing the clock signal in the second clock domain.

25. The method of claim 24 wherein the input clock signal is decoupled from the input before the output is decoupled.

26. The method of claim 24 wherein generating the clock signal in the second clock domain comprises:

recoupling the output to provide the clock signal in the second clock domain;

recoupling the input clock signal to the input of the adjustable delay circuit.

27. The method of claim 26 wherein the output is recoupled before the input clock signal is recoupled to the input of the adjustable delay circuit.

28. The method of claim 21 wherein generating a clock signal in the second clock domain comprises generating a clock signal having a frequency greater than the clock signal in the first clock domain and having a phase relationship relative to a rising edge of the clock signal in the first clock domain.