Voltage generation circuit and method thereof
First Claim
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1. A voltage generation circuit, comprising:
- a static current circuit, the static current circuit including,an operational amplifier including an inverted input terminal configured to receive a reference potential,a first PMOS transistor including a drain and gate connected to an non-inverted input terminal and an output node of the operational amplifier, respectively, and a source connected to a power source voltage, anda first resistor connected between the drain of the first PMOS transistor and a ground; and
a current mirror, the current mirror including,a second PMOS transistor including a source connected to the power source voltage and a gate connected to the gate of the first PMOS transistor,a first NMOS transistor including a drain and gate commonly connected to a drain of the second PMOS transistor,a second resistor connected between a source of the first NMOS transistor and the ground,a third PMOS transistor including a source connected to the power source voltage and a gate and drain connected to each other,a second NMOS transistor including a drain connected to the drain of the third PMOS transistor and a gate connected to the gate of the first NMOS transistor,a third resistor connected between a source of the second NMOS transistor and the ground, andan output terminal connected to the source of the second NMOS transistor.
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Abstract
A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.
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Citations
13 Claims
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1. A voltage generation circuit, comprising:
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a static current circuit, the static current circuit including, an operational amplifier including an inverted input terminal configured to receive a reference potential, a first PMOS transistor including a drain and gate connected to an non-inverted input terminal and an output node of the operational amplifier, respectively, and a source connected to a power source voltage, and a first resistor connected between the drain of the first PMOS transistor and a ground; and a current mirror, the current mirror including, a second PMOS transistor including a source connected to the power source voltage and a gate connected to the gate of the first PMOS transistor, a first NMOS transistor including a drain and gate commonly connected to a drain of the second PMOS transistor, a second resistor connected between a source of the first NMOS transistor and the ground, a third PMOS transistor including a source connected to the power source voltage and a gate and drain connected to each other, a second NMOS transistor including a drain connected to the drain of the third PMOS transistor and a gate connected to the gate of the first NMOS transistor, a third resistor connected between a source of the second NMOS transistor and the ground, and an output terminal connected to the source of the second NMOS transistor. - View Dependent Claims (2, 3, 4)
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5. A voltage generation circuit, comprising:
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a static current circuit, the static current circuit including, an operational amplifier including an inverted input terminal configured to receive a reference potential, a first PMOS transistor including a drain and gate connected to an non-inverted input terminal and an output node of the operational amplifier, respectively, and a source connected to a power source voltage, and a first resistor connected between the drain of the first PMOS transistor and a ground; a level shifter, the level shifter including, a fourth PMOS transistor including a source connected to the power source voltage and a gate connected to the gate of the first PMOS transistor, and a third NMOS transistor including a drain and gate commonly connected to a drain of the fourth PMOS transistor; and a current mirror, the current mirror including, a first NMOS transistor including a source connected to the ground and a gate connected to the gate of the third NMOS transistor, a second PMOS transistor including a drain and gate commonly connected to a drain of the first NMOS transistor, a second resistor connected between a source of the second PMOS transistor and the power source voltage, a second NMOS transistor including a source connected to the ground and a drain and gate connected to each other, a third PMOS transistor including a drain connected to the drain of the second NMOS transistor and a gate connected to the gate of the second PMOS transistor, a third resistor connected between a source of the third PMOS transistor and the power source voltage, an output terminal connected to the source of the third PMOS transistor. - View Dependent Claims (6, 7)
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8. A voltage generation circuit, comprising:
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a static current circuit configured to receive a reference potential, maintain a first current flowing through a first resistor, and output a first voltage; and a current mirror configured to receive the first voltage, maintain a second current flowing through a second resistor in response to the first voltage, the second current being equal to the first current, maintain a third current flowing through a third resistor in response to the first voltage, the third current being equal to a number n times the second current, n being larger than 1 , and output an output voltage equal to a voltage level of the voltage across terminals of the third resistor, wherein the static current circuit includes, an operational amplifier including an inverted input terminal configured to receive the reference potential, a first PMOS transistor including a drain and gate connected to an non-inverted input terminal and an output node of the operational amplifier, respectively, and a source connected to a power source voltage, wherein the first resistor is connected between the drain of the first PMOS transistor and a ground; and the current mirror includes, a second PMOS transistor including a source connected to the power source voltage and a gate connected to the gate of the first PMOS transistor, a first NMOS transistor including a drain and gate commonly connected to a drain of the second PMOS transistor, wherein the second resistor is connected between a source of the first NMOS transistor and the ground, and a third PMOS transistor including a source connected to the power source voltage and a gate and drain connected to each other, a second NMOS transistor including a drain connected to the drain of the third PMOS transistor and a gate connected to the gate of the first NMOS transistor, wherein the third resistor is connected between a source of the second NMOS transistor and the ground, and an output terminal connected to the source of the second NMOS transistor. - View Dependent Claims (9, 10, 11)
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12. A voltage generation circuit, comprising:
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a static current circuit configured to receive a reference potential, maintain a first current flowing through a first resistor, and output a first voltage; a current mirror configured to receive the first voltage, maintain a second current flowing through a second resistor in response to the first voltage, the second current being equal to the first current, maintain a third current flowing through a third resistor in response to the first voltage, the third current being equal to a number n times the second current, n being lager than 1, and output an output voltage equal to a voltage level of the voltage across terminals of the third resistor; a level shifter, wherein the static current circuit includes, an operational amplifier including an inverted input terminal configured to receive the reference potential, a first PMOS transistor including a drain and gate connected to an non-inverted input terminal and an output node of the operational amplifier, respectively, and a source connected to a power source voltage, wherein the first resistor is connected between the drain of the first PMOS transistor and a ground; the level shifter includes, a fourth PMOS transistor including a source connected to the power source voltage and a gate connected to the gate of the first PMOS transistor, and a third NMOS transistor including a drain and gate commonly connected to a drain of the fourth PMOS transistor; and the current mirror includes, a first NMOS transistor including a source connected to the ground and a gate connected to the gate of the third NMOS transistor, a second PMOS transistor including a drain and gate commonly connected to a drain of the first NMOS transistor, wherein the second resistor is connected between a source of the second PMOS transistor and the power source voltage, a second NMOS transistor including a source connected to the ground and a drain and gate connected to each other, a third PMOS transistor including a drain connected to the drain of the second NMOS transistor and a gate connected to the gate of the second PMOS transistor, wherein the third resistor is connected between a source of the third PMOS transistor and the power source voltage, and an output terminal connected to the source of the third PMOS transistor. - View Dependent Claims (13)
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Specification