Chopper-stabilized amplifier and magnetic field sensor

• US 7,605,647 B1
• Filed: 04/29/2008
• Issued: 10/20/2009
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Monreal, Gerardo, Romero, Hernan D.
• Primary Examiner(s): CHOE, HENRY
• Application Number:
  US12/111,554
• Publication Number:
  US 20090267687A1
• Time in Patent Office: 539 Days
• Field of Search: 330/6, 330/9, 327/124, 327/307
• US Class Current: 330/9
• CPC Class Codes: G01R 33/072 Constructional adaptation of the sensor to specific applications
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

A chopper-stabilized amplifier has switching networks arranged to support a high frequency clocking signal and to provide a high common mode rejection and a high rejection of an offset component of an input signal. A magnetic field sensor includes a Hall effect element coupled to a modulation circuit. The modulation circuit provides a signal to the chopper-stabilized amplifier. The chopper-stabilized amplifier provides an output signal to a low pass filter, which provides an output signal from the magnetic field sensor.

Claims

1. A chopper-stabilized amplifier, comprising:

first and second front-end amplifiers, each having a respective input node and each having a respective feedback node, wherein the first front-end amplifier is configured to generate a first amplified output signal and the second front-end amplifier is configured to generate a second amplified output signal;

a first switching network coupled to receive a binary clock signal having first and second periodic states, coupled to receive the first and second amplified output signals, and configured to generate first and second switched output signals, wherein, during the first state of the binary clock signal, the first switched output signal is related to the first amplified output signal and the second switched output signal is related to the second amplified output signal, and wherein, during the second state of the binary clock signal, the first switched output signal is related to the second amplified output signal and the second switched output signal is related to the first amplified output signal;

first and second back-end amplifiers, wherein the first back-end amplifier is coupled to receive the first switched output signal and the second back-end amplifier is coupled to receive the second switched output signal, wherein the first back-end amplifier is configured to generate a first back-end output signal and the second back-end amplifier is configured to generate a second back-end output signal, wherein an output signal of the chopper-stabilized amplifier is a differential signal comprised of the first and second back-end output signals; and

at least one of a feedback circuit or a second switching network coupled to receive the first and second back-end output signals, wherein the other one of the feedback circuit or the second switching network is configured to generate first and second switched feedback signals, wherein the second switching network is coupled to receive the binary clock signal, wherein, during the first state of the binary clock signal, the first switched feedback signal is related to the first back-end output signal and the second switched feedback signal is related to the second back-end output signal, and wherein, during the second state of the binary clock signal, the first switched feedback signal is related to the second back-end output signal and the second switched feedback signal is related to the first back-end output signal, wherein the feedback node of the first front-end amplifier is coupled to receive the first switched feedback signal, and wherein the feedback node of the second front-end amplifier is coupled to receive the second switched feedback signal.

2. The chopper-stabilized amplifier of claim 1, wherein the feedback circuit comprises first, second, and third series coupled resistors.

3. The chopper-stabilized amplifier of claim 2, wherein the third resistor comprises two series coupled resistors.

4. The chopper-stabilized amplifier of claim 1, wherein the input nodes of the first and second front-end amplifiers are coupled to receive a modulated differential input signal.

5. The chopper-stabilized amplifier of claim 4, wherein the first and second amplified output signals are differential signals and wherein the first and second switched output signals are differential signals.

6. The chopper-stabilized amplifier of claim 4, wherein the modulated differential input signal includes a modulated signal component and an un-modulated offset component.

7. The chopper-stabilized amplifier of claim 1, wherein the first and second back-end output signals include a modulated offset component and an un-modulated signal component.

8. The chopper-stabilized amplifier of claim 1, wherein the first and second front-end amplifiers have a relatively larger gain-bandwidth product, and wherein the first and second back-end amplifiers have a relatively lower gain-bandwidth product.

9. The chopper-stabilized amplifier of claim 8, wherein the first and second front-end amplifiers have a gain-bandwidth product in the range of about 100 kHz to 5 MHz.

10. The chopper-stabilized amplifier of claim 9, wherein the first and second back-end amplifiers have a gain-bandwidth product in the range of about 10 kHz to 500 kHz.

11. The chopper-stabilized amplifier of claim 9, wherein the first and second back-end amplifiers are Miller amplifiers, each having at least one respective pole in the frequency domain.

12. The chopper-stabilized amplifier of claim 1, wherein the binary clock signal has a frequency in a range of about 100 kHz to 1 MHz.

13. A magnetic field sensor, comprising:

a Hall effect element having two output nodes at which is provided a differential output signal that varies in response to a magnetic field, the Hall effect element differential output signal comprising a magnetic field signal component and an offset component; and

a chopper-stabilized amplifier, comprising;

first and second front-end amplifiers, each having a respective input node coupled to the Hall effect element and each having a respective feedback node, wherein the first front-end amplifier is configured to generate a first amplified output signal and the second front-end amplifier is configured to generate a second amplified output signal;

a first switching network coupled to receive a binary clock signal having first and second periodic states, coupled to receive the first and second amplified output signals, and configured to generate first and second switched output signals, wherein, during the first state of the binary clock signal, the first switched output signal is related to the first amplified output signal and the second switched output signal is related to the second amplified output signal, and wherein, during the second state of the binary clock signal, the first switched output signal is related to the second amplified output signal and the second switched output signal is related to the first amplified output signal;

first and second back-end amplifiers, wherein the first back-end amplifier is coupled to receive the first switched output signal and the second back-end amplifier is coupled to receive the second switched output signal, wherein the first back-end amplifier is configured to generate a first back-end output signal and the second back-end amplifier is configured to generate a second back-end output signal, wherein an output signal of the chopper-stabilized amplifier is a differential signal comprised of the first and second back-end output signals; and

at least one of a feedback circuit or a second switching network coupled to receive the first and second back-end output signals, wherein the other one of the feedback circuit or the second switching network is configured to generate first and second switched feedback signals, wherein the second switching network is coupled to receive the binary clock signal, wherein, during the first state of the binary clock signal, the first switched feedback signal is related to the first back-end output signal and the second switched feedback signal is related to the second back-end output signal, and wherein, during the second state of the binary clock signal, the first switched feedback signal is related to the second back-end output signal and the second switched feedback signal is related to the first back-end output signal, wherein the feedback node of the first front-end amplifier is coupled to receive the first switched feedback signal, and wherein the feedback node of the second front-end amplifier is coupled to receive the second switched feedback signal.

14. The magnetic field sensor of claim 13, further comprising a modulation circuit coupled between the Hall effect element and the chopper-stabilized amplifier and coupled to receive the binary clock signal, wherein the modulation circuit is operable to modulate the magnetic field signal component to provide to the first and second front-end amplifiers a modulated signal having the modulated magnetic field signal component and having an un-modulated offset component.

15. The magnetic field sensor of claim 14, wherein the modulation circuit is operable to modulate the magnetic field signal component in accordance with the frequency of the binary clock signal.

16. The magnetic field sensor of claim 14, wherein the feedback circuit comprises first, second, and third series coupled resistors.

17. The magnetic field sensor of claim 14, wherein the first and second amplified output signals are differential signals and wherein the first and second switched output signals are differential signals.

18. The magnetic field sensor of claim 14, wherein the first and second back-end output signals include a modulated offset component and a de-modulated magnetic field signal component.

19. The magnetic field sensor of claim 14, wherein the first and second front-end amplifiers have a relatively larger gain-bandwidth product, and wherein the first and second back-end amplifiers have a relatively lower gain-bandwidth product.

20. The magnetic field sensor of claim 19, wherein the first and second front-end amplifiers have a gain-bandwidth product in the range of about 100 kHz to 5 MHz.

21. The magnetic field sensor of claim 20, wherein the first and second back-end amplifiers have a gain-bandwidth product in the range of about 10 kHz to 500 kHz.

22. The magnetic field sensor of claim 19, wherein the first and second back-end amplifiers are Miller amplifiers, each having at least one respective pole in the frequency domain.

23. The magnetic field sensor of claim 14, wherein the binary clock signal has a frequency in a range of about 100 kHz to 1 MHz.