Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy

• US 7,605,650 B2
• Filed: 03/29/2008
• Issued: 10/20/2009
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US12/079,706
• Publication Number:
  US 20080186093A1
• Time in Patent Office: 570 Days
• Field of Search: 330/109, 330/98, 330/104
• US Class Current: 330/109
• CPC Class Codes: H03F 1/38 Positive-feedback circuit arrangements without negative feedback
• CPC Class Codes: H03F 2203/45514 the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

Claims

1. An amplifier circuit, comprising:

a first stage amplifier having an input terminal and an output terminal, the first stage amplifier being configured to operate with positive feedback;

a second stage amplifier having an input terminal and an output terminal, the input terminal of the second stage amplifier being coupled to the output terminal of the first stage amplifier, the first stage amplifier and the second stage amplifier together forming an inverting amplifier between the output terminal of the second stage amplifier and the input terminal of the first stage amplifier;

a first feedback capacitor connected between the output terminal of the second stage amplifier and the input terminal of the first stage amplifier, the first feedback capacitor being operable to provide negative feedback from the output terminal of the second stage amplifier to the input terminal of the first stage amplifier; and

a second feedback capacitor connected between the output terminal of the first stage amplifier and a non-inverting input terminal of the first stage amplifier, the second feedback capacitor being operable to provide positive feedback to the first stage amplifier.

2. The amplifier circuit of claim 1 wherein the first stage amplifier comprises:

an input transistor having a gate coupled to the input terminal of the first stage amplifier; and

a positive feedback transistor coupled in parallel with the input transistor, the positive feedback transistor having a gate coupled to a node of the first stage amplifier that is non-inverting with respect to the input signal applied to the input terminal of the first stage amplifier.

3. The amplifier circuit of claim 1 wherein the first stage amplifier comprises:

a first and a second CMOS transistors coupled to form a first path for a current to flow from a first potential, the second CMOS transistor having a gate coupled to the input terminal of the first stage amplifier;

a third and a fourth CMOS transistors coupled to form a second path for a current to flow from the first potential, the fourth CMOS transistor having a gate coupled to a first bias voltage, the first and third CMOS transistors being coupled together at their respective gates; and

a fifth CMOS transistor coupled to the second and fourth CMOS transistors and operable to receive the currents from the first and second paths and allow the currents to flow to the second potential.

4. The amplifier circuit of claim 3 wherein the fifth CMOS transistor is biased to allow a regulated current to flow through the fifth CMOS transistor.

5. The amplifier circuit of claim 3 wherein the first and the third CMOS transistors comprise PMOS-type transistors.

6. The amplifier circuit of claim 3 wherein the second, fourth and fifth CMOS transistors comprise NMOS-type transistors.

7. The amplifier circuit of claim 3 wherein the input capacitor is connected between the amplifier input terminal and a gate of the second transistor, and wherein a second feedback capacitor is connected between a drain of the fourth transistor and the gate of the second transistor.

8. The amplifier circuit of claim 3 wherein the first stage amplifier comprises a positive feedback transistor coupled in parallel with the second transistor, the positive feedback transistor having a gate coupled to the drain of the fourth transistor.

9. The amplifier circuit of claim 3 wherein the first and third CMOS transistors are configured to as a current mirror so that the magnitude of the current flowing through the first current path is equal to the current flowing through the second current path.

10. The amplifier circuit of claim 3 wherein the first potential comprises a power supply voltage.

11. The amplifier circuit of claim 3 wherein the second potential comprises ground potential.

12. The amplifier circuit of claim 3 wherein the first bias voltage comprises ground potential.

13. The amplifier circuit of claim 1 wherein the second stage amplifier comprises a unity gain inverting amplifier.

14. An amplifier circuit, comprising:

a first stage amplifier having an input terminal and an output terminal, the first stage amplifier being configured to operate with positive feedback;

an input capacitor connected between an amplifier input terminal and the input terminal of the first stage amplifier;

a second stage amplifier having an input terminal and an output terminal, the input terminal of the second stage amplifier being coupled to the output terminal of the first stage amplifier, the first stage amplifier and the second stage amplifier together forming an inverting amplifier between the output terminal of the second stage amplifier and the input terminal of the first stage amplifier; and

a first feedback capacitor connected between the output terminal of the second stage amplifier and the input terminal of the first stage amplifier, the first feedback capacitor being operable to provide negative feedback from the output terminal of the second stage amplifier to the input terminal of the first stage amplifier.

15. The amplifier circuit of claim 14 wherein the first stage amplifier comprises:

an input transistor having a gate coupled to the input terminal of the first stage amplifier; and

a positive feedback transistor coupled in parallel with the input transistor, the positive feedback transistor having a gate coupled to a node of the first stage amplifier that is non-inverting with respect to the input signal applied to the input terminal of the first stage amplifier.

16. The amplifier circuit of claim 14 wherein the first stage amplifier comprises:

a first and a second CMOS transistors coupled to form a first path for a current to flow from a first potential, the second CMOS transistor having a gate coupled to the input terminal of the first stage amplifier;

a third and a fourth CMOS transistors coupled to form a second path for a current to flow from the first potential, the fourth CMOS transistor having a gate coupled to a first bias voltage, the first and third CMOS transistors being coupled together at their respective gates; and

a fifth CMOS transistor coupled to the second and fourth CMOS transistors and operable to receive the currents from the first and second paths and allow the currents to flow to the second potential.

17. The amplifier circuit of claim 16 wherein the fifth CMOS transistor is biased to allow a regulated current to flow through the fifth CMOS transistor.

18. The amplifier circuit of claim 16 wherein the first and the third CMOS transistors comprise PMOS-type transistors.

19. The amplifier circuit of claim 16 wherein the second, fourth and fifth CMOS transistors comprise NMOS-type transistors.

20. The amplifier circuit of claim 16 wherein the input capacitor is connected between the amplifier input terminal and a gate of the second transistor, and wherein a second feedback capacitor is connected between a drain of the fourth transistor and the gate of the second transistor.

21. The amplifier circuit of claim 16 wherein the first stage amplifier comprises a positive feedback transistor coupled in parallel with the second transistor, the positive feedback transistor having a gate coupled to the drain of the fourth transistor.

22. The amplifier circuit of claim 16 wherein the first and third CMOS transistors are configured to as a current mirror so that the magnitude of the current flowing through the first current path is equal to the current flowing through the second current path.

23. The amplifier circuit of claim 16 wherein the first potential comprises a power supply voltage.

24. The amplifier circuit of claim 16 wherein the second potential comprises ground potential.

25. The amplifier circuit of claim 16 wherein the first bias voltage comprises ground potential.

26. The amplifier circuit of claim 14 wherein the second stage amplifier comprises a unity gain inverting amplifier.