Cache hit logic of cache memory and processor chip having the same

• US 7,606,054 B2
• Filed: 02/02/2007
• Issued: 10/20/2009
• Est. Priority Date: 05/28/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kwang-Il
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/701,674
• Publication Number:
  US 20070139991A1
• Time in Patent Office: 991 Days
• Field of Search: 365/49, 365/189.07, 365/185.2, 365/189.05, 365/189.11
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Abstract

A processor chip having a cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparison logic for determining whether the sensed tag address coincides with an input tag address, a dummy sense amplifier, and a dummy comparison logic. The processor chip having the cache hit logic improves the reliability of a hit signal and operation speed is not limited.

Claims

1. A data processing system comprising:

a processor; and

a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein

the cache hit logic includes;

a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses;

a row decoder for selecting the rows;

a column decoder for selecting the columns;

a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal; and

a comparison circuit for comparing the sensed tag address with an input tag address when a time required for the sense amplifier to sense the tag address has passed after the enable signal is activated, to output a hit signal corresponding to the comparison result, wherein the comparison circuit activates an output enable signal when a time required for the sense amplifier to sense the tag address has passed after the enable signal is activated.

2. The data processing system as set forth in claim 1, wherein the cache memory further comprises:

a data memory storing the data to be used at the processor,

the data memory supplying data to the processor in response to the determination result of the cache hit logic.

3. The data processing system as set forth in claim 1, wherein the cache memory further comprises:

a plurality of cache hit logics;

a data memory divided into a plurality of ways and storing the data to be used at the processor; and

a way selector selectively supplying data of ways of the data memory to the processor in response to the determination result of the cache hit logic.

4. The data processing system as set forth in claim 1, wherein the comparison circuit comprises:

a dummy cell string having dummy cells arranged in a line in a column direction;

a dummy sense amplifier for sensing a dummy address stored in a cell of the dummy cell string selected by the row decoder in response to the enable signal; and

a logic circuit for activating the output enable signal when a pair of complementary dummy address bits are output from the dummy sense amplifier.

5. The data processing system as set forth in claim 1, wherein the dummy cell string is a static random access memory(SRAM) cell string.

6. The data processing system as set forth in claim 1, wherein the cache memory further comprises a logic circuit for comparing the sensed tag address with the input tag address to output a comparison signal.

7. A data processing system comprising:

a processor; and

a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein

the cache hit logic includes;

a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses;

a row decoder for selecting the rows;

a column decoder for selecting the columns;

a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal;

a comparison circuit for comparing the sensed tag address with an input tag address;

a dummy cell string having dummy cells arranged in a column direction of the tag memory cell array;

a dummy sense amplifier for sensing a dummy address stored in a dummy cell selected by the row decoder in response to the activation of the enable signal; and

an output circuit for outputting the comparison signal from the comparison logic as a hit signal when the dummy sense amplifier senses the dummy address.

8. The data processing system as set forth in claim 7, wherein the dummy cell string is a static random access memory(SRAM) cell string.

9. The data processing system as set forth in claim 8, wherein the dummy sense amplifier senses a pair of complementary dummy address bits.

10. The data processing system as set forth in claim 9, wherein the output circuit comprises:

a dummy comparison logic for comparing the pair of complementary dummy address bits sensed by the dummy sense amplifier with each other to output a dummy comparison signal; and

an output portion for outputting the comparison signal from the comparison logic as the hit signal in response to the dummy comparison signal.

11. The data processing system as set forth in claim 10, wherein the comparison logic and the dummy comparison logic are composed of the same circuit.

12. A data processing system comprising:

a processor; and

a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein

the cache hit logic includes;

a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses;

a row decoder for selecting the rows;

a column decoder for selecting the columns;

a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal;

a comparison circuit for comparing the sensed tag address with an input tag address;

a dummy sense amplifier for receiving a source voltage and a ground voltage to output a pair of complementary dummy address bits in response to the activation of the enable signal; and

an output circuit for outputting the comparison signal from the comparison logic as a hit signal when the dummy sense amplifier outputs the pair of complementary dummy address bits.

13. The data processing system as set forth in claim 12, wherein the output circuit comprises:

a dummy comparison logic for comparing the pair of complementary dummy address bits output from the dummy sense amplifier with each other to output a dummy comparison signal; and

an output portion for outputting the comparison signal from the comparison logic as the hit signal in response to the dummy comparison signal.

14. The data processing system as set forth in claim 13, wherein the comparison logic and the dummy comparison logic are composed of the same circuit.

15. A cache hit detection method in a cache memory having a tag memory cell array which stores a tag address and is composed of tag memory cells arranged in rows and columns, the method comprising:

(a) sensing the tag address of the tag memory cell corresponding to a selected row and column in response to an enable signal;

(b) comparing the sensed tag address with an input tag address;

(c) activating an output enable signal when a time required for the sense amplifier to sense the tag address of the tag memory cell has passed; and

(d) outputting a hit signal corresponding to the comparison result in response to the output enable signal.

16. The cache hit detection method in a cache memory as set forth in claim 15, wherein comparing the sensed tag address further comprises determining whether the sensed tag address coincides with the input tag address, to output the determination result.

17. A cache hit detection method in a cache memory having a tag memory cell array which stores a tag address and is composed of tag memory cells arranged in rows and columns, the method comprising:

(a) sensing the tag address of the tag memory cell corresponding to a selected row and column in response to an enable signal;

(b) sensing the dummy address of the dummy cell corresponding to the selected row in response to the enable signal;

(c) comparing the sensed tag address with an input tag address;

(d) activating an output enable signal in response to the sensed dummy address when a time required for the sense amplifier to sense the tag address of the tag memory cell has passed; and

(e) outputting a hit signal corresponding to the comparison result in response to the output enable signal.

18. The cache hit detection method in a cache memory as set forth in claim 17, wherein the dummy cell is a static random access memory(SRAM) cell string.

19. The cache hit detection method in a cache memory as set forth in claim 17, wherein comparing the sensed tag address further comprises outputting the comparison result of the sensed tag address with an input tag address.

20. The cache hit detection method in a cache memory as set forth in claim 17, wherein the dummy address is a pair of complementary dummy addresses.

21. A cache hit detection method in a cache memory having a tag memory cell array which stores a tag address and is composed of tag memory cells arranged in rows and columns, the method comprising:

(a) sensing the tag address of the tag memory cell corresponding to a selected row and column in response to an enable signal;

(b) sensing the dummy address of the dummy cell in response to the enable signal;

(c) comparing the sensed tag address with an input tag address;

(d) activating an output enable signal in response to the sensed dummy address when a time required for the sense amplifier to sense the tag address of the tag memory cell has passed; and

(e) outputting a hit signal corresponding to the comparison result in response to the output enable signal.

22. The cache hit detection method in a cache memory as set forth in claim 21, wherein the dummy cell is composed of a power source voltage and a ground voltage.

23. The cache hit detection method in a cache memory as set forth in claim 21, wherein comparing the sensed tag address further comprises outputting the comparison result of the sensed tag address with an input tag address.