Eight transistor SRAM cell with improved stability requiring only one word line

• US 7,606,060 B2
• Filed: 08/01/2007
• Issued: 10/20/2009
• Est. Priority Date: 01/18/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuen H., Plass, Donald W., Huott, William V.
• Primary Examiner(s): Luu; Pho M.
• Application Number:
  US11/832,190
• Publication Number:
  US 20090034345A1
• Time in Patent Office: 811 Days
• Field of Search: 365/154, 365/155, 365/156
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

Claims

1. A static random access memory comprising in combination:

a plurality of bi-stable memory cells arranged in rows and columns;

a pair of write bit lines common to each memory cell in a column;

a single pre-charged read bit line common to each memory cell in a column;

each cell including a pair of write data field effect transistors respectively connecting said each cell in column to said pair of write bit lines, a gate of each of said pair connected respectively to said pair of write bit lines for writing data into each cell;

a single read data field effect transistor connecting said each cell to said read bit line, with its gate coupled to a node of said each cell in a column for reading data from said cell;

a single field effect transistor connected to said pair of write data field effect transistors and said read data field effect transistor with its gate coupled to a single word line to control both read access and write access to said each cell.

2. A static random access memory as in claim 1 wherein:

said pair of write data field effect transistors are each n-type field effect transistors;

said read data field effect transistor is an n-type field effect transistor, and

said single field effect transistor is an n-type field effect transistor.