Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells

• US 7,606,100 B2
• Filed: 02/29/2008
• Issued: 10/20/2009
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Hemink, Gerrit Jan, Kamei, Teruhiko
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US12/040,632
• Publication Number:
  US 20080158997A1
• Time in Patent Office: 599 Days
• Field of Search: 365/218, 365/185.17, 365/185.22, 365/185.29, 365/185.18
• US Class Current: 365/218
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.

Claims

1. A method of erasing non-volatile storage, comprising:

applying an erase voltage to a set of non-volatile storage elements while enabling erasing of each non-volatile storage element in said set, said set including a first subset of non-volatile storage elements and a second subset of non-volatile storage elements;

verifying whether said set is erased after applying said erase voltage by testing conduction through said set while applying a verify voltage to said first subset of non-volatile storage elements and applying a first voltage to said second subset of non-volatile storage elements, said first voltage is different from said verify voltage;

repeating said applying said erase voltage and verifying whether said set is erased until successfully verifying that said set is erased; and

applying said erase voltage to said set while inhibiting erasing of said first subset after successfully verifying that said set is erased.

2. A method according to claim 1, further comprising:

verifying whether said set is erased after said applying said erase voltage to said set while inhibiting erasing of said first subset; and

repeating said applying said erase voltage to said set while inhibiting erasing of said first subset and said verifying whether said set is erased after applying said erase voltage to said set while inhibiting erasing of said first subset until successfully verifying that said set is erased.

3. A method according to claim 2, wherein:

verifying whether said set is erased after applying said erase voltage to said set while inhibiting erasing of said first subset includes testing conduction through said set while applying said verify voltage to said first subset and said second subset.

4. A method according to claim 2, wherein:

verifying whether said set is erased after applying said erase voltage to said set while inhibiting erasing of said first subset includes testing conduction through said set while applying said verify voltage to said second subset and said first voltage to said first subset.

5. A method according to claim 4, wherein:

said first voltage is larger than said verify voltage; and

said applying said first voltage to said second subset promotes conduction of each non-volatile storage element in said second subset.

6. A method according to claim 1, wherein repeating said applying said erase voltage and verifying whether said set is erased includes increasing a size of said erase voltage between each application of said erase voltage.

7. A method according to claim 1, wherein said set of non-volatile storage elements is part of a NAND string.

8. A method according to claim 7, wherein:

said NAND string includes a first select gate and a second select gate;

said second subset of non-volatile storage elements includes a first non-volatile storage element adjacent to said first select gate and a second non-volatile storage element adjacent to said second select gate; and

said first subset of non-volatile storage elements includes a plurality of non-volatile storage elements between said first non-volatile storage element and said second non-volatile storage element.

9. A method of erasing non-volatile storage, comprising:

applying an erase voltage to a set of non-volatile storage elements while enabling erasing of each non-volatile storage element of said set, said set including a first subset of non-volatile storage elements and a second subset of non-volatile storage elements;

verifying whether said set is erased after applying said erase voltage by causing said second subset of non-volatile storage elements to be conductive and testing conduction through said set while applying a verify voltage to said first subset of non-volatile storage elements;

repeating said applying said erase voltage and verifying whether said set is erased until successfully verifying that said set is erased; and

applying said erase voltage to said set while inhibiting erasing of said first subset of non-volatile storage elements after successfully verifying that said set is erased.

10. A method according to claim 9, wherein:

causing said second subset of non-volatile storage elements to be conductive includes applying a first voltage that is larger than said verify voltage to said second subset of non-volatile storage elements, said first voltage promotes conduction of each non-volatile storage element in said second subset of non-volatile storage elements.

11. A method according to claim 10, further comprising:

verifying whether said set is erased after applying said erase voltage to said set while inhibiting said first subset of non-volatile storage elements from being erased; and

repeating said applying said erase voltage to said set while inhibiting erasing of said first subset and said verifying whether said set is erased after applying said erase voltage to said set while inhibiting said first subset of from being erased until successfully verifying that said set is erased.

12. A method according to claim 11, wherein:

verifying whether said set is erased after applying said erase voltage to said set while inhibiting said first subset from being erased includes testing conduction through said set while applying said verify voltage to said first subset and said second subset.

13. A method according to claim 11, wherein:

verifying whether said set is erased after applying said erase voltage to said set while inhibiting said first subset from being erased includes testing conduction through said set while applying said verify voltage to said second subset and applying said first voltage to said first subset of non-volatile storage elements, said first voltage promotes conduction of each non-volatile storage element in said first subset.

14. A method according to claim 9, wherein:

said set of non-volatile storage elements is part of a NAND string; and

said NAND string includes a first select gate and a second select gate;

said second subset of non-volatile storage elements includes a first non-volatile storage element adjacent to said first select gate and a second non-volatile storage element adjacent to said second select gate; and

said first subset of non-volatile storage elements includes a plurality of non-volatile storage elements between said first non-volatile storage element and said second non-volatile storage element.

15. A method of erasing non-volatile storage, comprising:

applying an erase voltage to a block of non-volatile storage elements in communication with a set of word lines, said block including a plurality of sets of series-connected non-volatile storage elements;

verifying whether said sets of non-volatile storage elements are erased after applying said erase voltage by applying a verify voltage to a first subset of said set of word lines and a first voltage to a second subset of said set of word lines, said first voltage is different from said verify voltage;

repeating said applying and said verifying until all or a predetermined number of said sets of non-volatile storage elements are successfully verified as erased; and

applying said erase voltage to said block of non-volatile storage elements while inhibiting erasing of non-volatile storage elements in communication with said first subset of word lines after successfully verifying that all or said predetermined number of said sets of non-volatile storage elements are erased.

16. A method according to claim 15, further comprising:

verifying whether said sets of series-connected non-volatile storage elements are erased after said applying said erase voltage to said block while inhibiting erasing of non-volatile storage elements in communication with said first subset of word lines; and

repeating said applying said erase voltage to said block while inhibiting erasing of non-volatile storage elements in communication with said first subset of word lines and said verifying whether said sets are erased after said applying said erase voltage to said block while inhibiting erasing of non-volatile storage elements in communication with said first subset of word lines until all or a predetermined number of said sets are successfully verified as erased.

17. A method according to claim 16, wherein verifying whether said sets of series-connected non-volatile storage elements are erased after said applying said erase voltage to said block while inhibiting erasing of non-volatile storage elements in communication with said first subset of word lines includes:

testing conduction through said sets of series-connected non-volatile storage elements while applying said verify voltage to said first subset of word lines and said second subset of word lines.

18. A method according to claim 16, wherein verifying whether said sets of series-connected non-volatile storage elements are erased after said applying said erase voltage to said block while inhibiting erasing of non-volatile storage elements in communication with said first subset of word lines includes:

testing conduction through said sets of series-connected non-volatile storage elements while applying said verify voltage to said second subset of word lines and said first voltage to said first subset of word lines.

19. A method according to claim 18, wherein:

said first voltage is larger than said verify voltage; and

said applying said first voltage to said first subset of word lines promotes conduction of non-volatile storage elements in communication with said first subset of word lines.

20. A method according to claim 16, wherein:

said sets of series-connected non-volatile storage elements are sets of NAND strings;

said NAND strings each include a first select gate in communication with a first select line and a second select gate in communication with a second select line;

said second subset of word lines includes a first word line adjacent to said first select line and a second word line adjacent to said second select line; and

said first subset of word lines includes a plurality of word lines between said first word line and said second word line.