Decoding method and apparatus

• US 7,606,296 B1
• Filed: 06/11/2007
• Issued: 10/20/2009
• Est. Priority Date: 11/29/2001
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Hsu, Yungping, Xu, Nelson, Cheung, Ricky
• Primary Examiner(s): Fan; Chieh M
• Assistant Examiner(s): Ghulamali; Qutbuddin
• Application Number:
  US11/811,513
• Time in Patent Office: 862 Days
• Field of Search: 375/150, 375/133, 375/147, 375/148, 375/233, 375/343, 375/350, 375/371, 455/277.1, 370/335, 370/334, 370/441, 370/447
• US Class Current: 375/150
• CPC Class Codes: H04L 2025/03401 PSK
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A decoder comprises an equalizer that receives a modulated signal comprising a plurality of symbols including a first symbol defined by a first number of chips. A subsymbol processor that generates a subsymbol waveform after receiving a second number of chips of the first symbol and before at least one of receiving, decoding, and deciding the first number of chips of the first symbol. The second number is less than the first number, and wherein the equalizer equalizes the modulated signal using the subsymbol waveform.

Claims

1. A decoder, comprising:

an equalizer that receives a modulated signal comprising a plurality of symbols including a first symbol defined by a first number of chips; and

a subsymbol processor that generates a subsymbol waveform after receiving a second number of chips of the first symbol and before at least one of receiving, decoding, and deciding the first number of chips of the first symbol with the subsymbol processor,

wherein the second number is less than the first number, and wherein the equalizer equalizes the modulated signal using the subsymbol waveform.

2. The decoder of claim 1 wherein the subsymbol waveform includes a third number of chips that is less than or equal to the second number of chips.

3. The decoder of claim 1 wherein the equalizer further comprises:

a hard decision unit that determines hard decision information associated with the modulated signal; and

a feedback filter that selectively equalizes the modulated signal using the hard decision information and the subsymbol waveform.

4. The decoder of claim 1 wherein the symbol is modulated in accordance with one of Barker spreading and complementary code keying (CCK).

5. The decoder of claim 1 further comprising:

a demodulation unit that generates decoded subsymbol information based on the second number of chips of the symbol; and

a remodulation unit that generates a subsymbol waveform corresponding to the decoded subsymbol information.

6. The decoder of claim 5 wherein the demodulation unit further comprises a symbol correlator that correlates the received second number of chips with a subset of valid candidate symbols to obtain a best match candidate, wherein the demodulation unit generates the decoded subsymbol information based on the best match candidate.

7. The decoder of claim 5 wherein the demodulation unit decides the symbol upon receipt of the first number of chips defining the symbol.

8. The decoder of claim 7 wherein the demodulation unit comprises first and second demodulation pathways that decide the symbol using at least one of first and second distinct modulation modes.

9. The decoder of claim 8 wherein the first and second distinct modulation modes comprise Barker spreading and complementary code keying.

10. A transceiver, comprising:

an equalizer that receives a modulated signal comprising a plurality of symbols including a first symbol defined by a first number of chips; and

a subsymbol processor that generates a subsymbol waveform after receiving a second number of chips of the first symbol and before at least one of receiving, decoding, and deciding the first number of chips of the first symbol with the subsymbol processor,

wherein the second number is less than the first number and wherein the equalizer equalizes the modulated signal using the subsymbol waveform.

11. The transceiver of claim 10 wherein the subsymbol waveform includes a third number of chips that is less than or equal to the second number of chips.

12. The transceiver of claim 10 wherein the equalizer comprises:

a hard decision unit that determines hard decision information associated with the modulated signal; and

a feedback filter that selectively equalizes the modulated signal using the hard decision information and the subsymbol waveform.

13. The transceiver of claim 10 wherein the symbol is modulated in accordance with one of Barker spreading and complementary code keying (CCK).

14. The transceiver of claim 10 further comprising RF and IF sections coupled to the equalizer to provide the modulated signal to the equalizer.

15. A base station comprising the transceiver of claim 14.

16. A network card comprising the transceiver of claim 14.

17. An information processing system comprising the transceiver of claim 10.

18. The transceiver of claim 10 further comprising:

a demodulation unit that generates decoded subsymbol information based on the second number of chips of the symbol; and

a remodulation unit that generates a subsymbol waveform corresponding to the decoded subsymbol information.

19. The transceiver of claim 18 wherein the demodulation unit further comprises a symbol correlator that correlates the second number of chips against a subset of valid candidate symbols to obtain a best match candidate, wherein the demodulation unit generates the decoded subsymbol information based on the best match candidate.

20. The transceiver of claim 18 wherein the demodulation unit decides the symbol after receiving the first number of chips defining the symbol.

21. The transceiver of claim 20 wherein the demodulation unit comprises first and second demodulation pathways that decide the symbol by at least one of first and second distinct modulation modes.

22. The transceiver of claim 21 wherein the first and second distinct modulation modes comprise Barker spreading and complementary code keying (CCK).

23. A decoder, comprising:

an equalizer that receives a modulated signal including a Barker encoded symbol defined by a first number of chips; and

a subsymbol processor that generates a decoded waveform upon receipt of a second number of chips of the symbol and before at least one of receiving, decoding, and deciding the first number of chips of the symbol with the subsymbol processor,

wherein the equalizer equalizes the modulated signal using the decoded waveform and wherein the first number is less than the second number.

24. The decoder of claim 23 wherein the modulated signal further includes a non-Barker encoded symbol defined by the second number of chips.

25. The decoder of claim 24 wherein the non-Barker encode symbol comprises a CCK encoded symbol.

26. A transceiver comprising the decoder of claim 25.

27. A base station comprising the transceiver of claim 26.

28. A network card comprising the transceiver of claim 26.

29. An information processing system comprising the transceiver of claim 26.

30. A decoder comprising:

an equalizer that receives a modulated signal including a received symbol defined by a first number of chips;

a demodulation unit comprising;

a decoder that decodes the received symbol after receiving the first number of chips defining the received symbol; and

partial correlation logic that generates a decoded subsymbol based on a second number of chips of the received symbol received by the equalizer and before at least one of receiving, decoding, and deciding the first number of chips of the received symbol, wherein the second number is less than the first number; and

a remodulation unit that generates a subsymbol waveform corresponding to the decoded subsymbol,

wherein the equalizer equalizes the remodulated signal using the subsymbol waveform.

31. The decoder of claim 30 wherein the subsymbol waveform includes a third number of chips corresponding to the subsymbol waveform, wherein the third number is less than or equal to the second number, and wherein the partial correlation logic generates the decoded subsymbol using correlation processing based on the second number of chips.

32. The decoder of claim 30 wherein the equalizer comprises:

a hard decision unit that determines hard decision information associated with the modulated signal; and

a feedback filter that equalizes the modulated signal using one of the hard decision information and the subsymbol waveform.

33. The decoder of claim 30 wherein the decoder of the demodulation unit comprise first and second demodulator units that decode the received symbol by at least one of first and second distinct modulation modes.

34. The decoder of claim 33 wherein the first and second distinct modulation modes comprise Barker spreading and complementary code keying.