Viterbi decoder using circulation type decoding units connected in parallel

• US 7,606,336 B2
• Filed: 01/31/2006
• Issued: 10/20/2009
• Est. Priority Date: 02/01/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Hong-rak, Kim, Hyun-jung, Lee, Jeong-won, Kim, Hyong-suk
• Primary Examiner(s): Torres; Juan A
• Application Number:
  US11/342,566
• Publication Number:
  US 20060171490A1
• Time in Patent Office: 1,358 Days
• Field of Search: 375/341, 714/794, 714/795
• US Class Current: 375/341
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording
• CPC Class Codes: H03M 13/6597 Implementations using analogue techniques for coding or decoding, e.g. analogue Viterbi decoder

Abstract

An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.

Claims

1. An analog Viterbi decoder, comprising:

a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells that are vertically arranged so as to correspond to respective nodes on a trellis diagram, each of the plurality of decoding units decoding analog input data using an analog signal processing cell having a circulation type connection structure in which a last processing part is connected to a first processing part;

a control unit that performs in parallel a sequential designation of the plurality of processing parts with respect to the plurality of decoding units in accordance with an external input clock signal;

an analog data storage unit including a plurality of capacitors connected in parallel with the plurality of processing parts that are provided in the plurality of decoding units; and

a first switch unit that stores analog input data in a specific capacitor of the analog data storage unit that is controlled by the control unit,

wherein the plurality of decoding units comprises a first decoding unit and a second decoding unit, and

wherein the sequential designation of the plurality of processing parts with respect to the plurality of decoding units comprises designating the first decoding unit to start decoding a specified bit of the analog input data using the first processing part of the first decoding unit, and designating the second decoding unit to start decoding a next bit of the analog input data using a second processing part of the second decoding unit, said first and second processing parts being among the plurality of processing parts.

2. The analog Viterbi decoder as claimed in claim 1, wherein the plurality of decoding units receive the analog data that is stored in the specific capacitor among the plurality of capacitors through specified processing parts provided in the plurality of decoding units, and decode the analog data in parallel.

3. The analog Viterbi decoder as claimed in claim 2, wherein the decoding unit comprises:

a cell selection unit that designates a specified cell among the cells of the processing part that is designated by the control unit;

a second switch unit, connected to respective processing parts of the analog signal processing cell, that applies a reference input signal to the specified cell that is designated by the control unit and the cell selection unit;

a maximum value operation unit that detects a maximum value among output values of the cells if the cells of the processing part that is designated output specified operation values using the reference input signal and an input value that is input from a previous processing part;

a third switch unit that detects an output signal of the maximum value operation unit;

a signal change sensing unit that senses a change of the output value by monitoring the signal that is output from the third switch unit; and

a pulse generation unit that outputs the change of the output value that is sensed by the signal change sensing unit as a pulse signal.

4. The analog Viterbi decoder as claimed in claim 3, wherein the control unit selects one of even-numbered cells and odd-numbered cells among the cells of the specified processing part that are included in each of the plurality of decoding units and initiates decoding operation from the decoding unit that is selected.

5. The analog Viterbi decoder as claimed in claim 4, wherein cells of a specified processing part that are included in each of the plurality of the decoding units calculate the output value using the following equation,

y_i,j=max{u_i,j,y_k,l−

d_ij,kl;

(k,l)∈

S(i,j)}

y_i,j=I_ref−

D_i,j

u_i,j=I_ref;

if (i,j) is the cell of the destination

u_i,j=0;

if (i,j) is not the cell of the destination

where, y_i,j denotes an output value of a cell (i, j), D_i,j denotes the shortest distance between the cell (i, j) and a destination cell, I_ref denotes a reference input signal value, d_i,j,kl denotes a partial distance from the cell (i, j) to a cell (k, l), S(i, j) denotes a set of cells that belong to an identical processing part as the cell (i, j), and max denotes a function that outputs a maximum value among enumerated items.

6. A decoder, comprising:

a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells that are arranged to correspond to respective nodes on a trellis diagram, each of the plurality of decoding units decoding input data using a signal processing cell having a circulation type connection structure in which a last processing part is connected to a first processing part;

a control unit that performs in parallel a sequential designation of the plurality of processing parts with respect to the plurality of decoding units; and

a data storage unit including a plurality of storage devices connected in parallel with the plurality of processing parts that are provided in the plurality of decoding units,

wherein the plurality of decoding units comprises a first decoding unit and a second decoding unit, and

wherein the sequential designation of the plurality of processing parts with respect to the plurality of decoding units comprises designating the first decoding unit to start decoding a specified bit of the input data using the first processing part of the first decoding unit, and designating the second decoding unit to start decoding a next bit of the input data using a second processing part of the second decoding unit, said first and second processing parts being among the plurality of processing parts.

7. The decoder as claimed in claim 6, further comprising a switch unit that stores analog input data in a specific storage device of the data storage unit under the control of the control unit.