Adaptable datapath for a digital processing system
First Claim
1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:
- a plurality of functional units for performing a digital operation;
a plurality of data address generators coupled to the memory bus;
a configurable data path configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between and among the plurality of data address generators and the plurality of functional units, the configurable data path including the configured or reconfigured interconnections for the data path configuration; and
wherein the plurality of data address generators are coupled between the memory bus and the configurable data path, each of the plurality of data address generators is configurable in response to a second, different configuration information to generate and control memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration.
4 Assignments
0 Petitions
Accused Products
Abstract
The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.
-
Citations
17 Claims
-
1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:
-
a plurality of functional units for performing a digital operation; a plurality of data address generators coupled to the memory bus; a configurable data path configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between and among the plurality of data address generators and the plurality of functional units, the configurable data path including the configured or reconfigured interconnections for the data path configuration; and wherein the plurality of data address generators are coupled between the memory bus and the configurable data path, each of the plurality of data address generators is configurable in response to a second, different configuration information to generate and control memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A digital processing system comprising:
-
a memory bus coupled to a memory; and a reconfigurable data path circuit coupled to the memory bus for obtaining data from the memory, the reconfigurable data path circuit comprising; a plurality of functional units for performing a digital operation; and a plurality of data address generators coupled to the memory bus; a configurable data path configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between and among the plurality of data address generators and the plurality of functional units, the configurable data path including the configured or reconfigured interconnections for the data path configuration; and wherein the plurality of data address generators are coupled between the memory bus and the configurable data path, and each of the plurality of data address generators is configurable in response to a second, different configuration information to generate and control memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration.
-
Specification