12C slave device with programmable write-transaction cycles

• US 7,606,956 B2
• Filed: 05/01/2006
• Issued: 10/20/2009
• Est. Priority Date: 04/29/2005
• Status: Active Grant

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Deshpande, Amrita, Anderson, Alma, Irazabal, Jean-Marc, Blozis, Stephen, Boogaards, Paul
• Primary Examiner(s): Stiglic; Ryan M
• Application Number:
  US11/913,057
• Publication Number:
  US 20080189458A1
• Time in Patent Office: 1,268 Days
• Field of Search: 710/104, 710/110
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers. Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its programmable register.

Claims

1. In a communications system using an Inter-Integrated Circuit (I²C) serial data transfer bus that has a serial data line and a clock line used to implement a communications protocol, a slave device, comprising:

input circuitry configured to receive serial data using the serial data transfer bus and provide data words assembled from the serial data;

a programmable register configured to be programmed, using the communications protocol, to select one or more slave device configurations; and

at least two banks of output drivers, configured to receive assembled data words provided by the input circuitry, wherein each bank of the at least two banks of output drivers updates its output drivers either sequentially, or in coordination with other of the at least two banks of output drivers, based on the slave device configuration selected by the programmable register.

2. The device of claim 1, wherein the slave device is configured as a general purpose Input/Output device.

3. The device of claim 1, wherein the at least two banks of output drivers update within one clock cycle when the slave device configuration is selected for coordinated writing.

4. The device of claim 1, wherein each bank of the at least two banks of output drivers updates its output drivers in response to an acknowledge signal from the input circuitry when the slave device configuration is selected for sequential writing.

5. The device of claim 1, wherein each bank of the at least two banks of output drivers updates its output drivers in response to a stop condition on the I²C bus when the slave device configuration is selected for coordinated writing.

6. In a communications system using an I²C serial data transfer bus that has a serial data line and a clock line used to implement a communications protocol, a method for a slave device to update at least two banks of output drivers in the slave device, comprising:

programming a register in the slave device, using the communications protocol, to designate whether the at least two banks of output drivers are to update sequentially or to update in parallel;

receiving serial data using the serial data transfer bus;

assembling one or more data words from the serial data; and

updating the at least two banks of output drivers using the assembled one or more data words, each bank updating either sequentially or in parallel relative to other banks, based on the programmed register.

7. The method of claim 6, wherein the serial data transfer bus further conforms to an SMBus serial communication specification.

8. The method of claim 6, wherein the slave device is configured as a general purpose Input/Output device.

9. The method of claim 6, wherein the at least two banks of output drivers update within one clock cycle when the slave device is programmed for parallel writing.

10. The method of claim 6, wherein each bank of the at least two banks of output drivers writes in response to an acknowledge signal when the register is programmed for sequential writing.

11. The method of claim 6, wherein each bank of the at least two banks of output drivers writes in response to a stop condition on the I²C bus when the register is programmed for coordinated writing.

12. A communications system using an I²C serial data transfer bus that has a serial data line and a clock line used to implement a communications protocol, the communications system comprising:

two or more slave devices, each slave device comprising;

input circuitry configured to receive serial data using the serial data transfer bus and provide a data word assembled from the serial data;

a programmable register configured to be programmed, using the communications protocol, to select one or more slave device configurations; and

at least one bank of output drivers, configured to output the assembled data word provided by the input circuitry; and

wherein each of the two or more slave devices updates its output drivers either sequentially, or in coordination with other of the two or more slave devices, based on each slave devices configuration selected by its programmable register.

13. The device of claim 12, wherein the two or more slave devices are configured as general purpose Input/Output devices.

14. The device of claim 12, wherein the two or more slave devices update within one clock cycle when the slave device configuration is selected for coordinated writing.

15. The device of claim 12, wherein the two or more slave devices update their output drivers in response to an acknowledge signal from the input circuitry when the slave device configuration is selected for sequential writing.

16. The device of claim 12, wherein the two or more slave devices update their output drivers in response to a stop condition on the I2C bus when the slave device configuration is selected for coordinated writing.