Apparatus for adjusting a clock frequency of a variable speed bus

• US 7,606,960 B2
• Filed: 03/26/2004
• Issued: 10/20/2009
• Est. Priority Date: 03/26/2004
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Munguia, Peter R.
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US10/810,026
• Publication Number:
  US 20050216643A1
• Time in Patent Office: 2,034 Days
• Field of Search: 710/33, 710/300, 710/307, 710/58, 710/240, 710/309, 710/15, 710/60, 710/313, 710/306, 713/600, 713/501, 713/320, 713/322, 340/825, 370/257, 709/233, 322/32, 361683-686, 712/32
• US Class Current: 710/307
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor and increases or decreases the bus frequency in order to meet the bandwidth levels requested. When the bandwidth requirements increase, the bus frequency increases. When the bandwidth requirements are reduced, the bus frequency is reduced to reduce power consumption. No software intervention is required to adjust the bus bandwidth.

Claims

1. An apparatus comprising:

a variable speed bus, the variable speed bus initialized with a first clock frequency;

a first unit coupled to the variable speed bus, the first unit having a first rate of requests to access the variable speed bus;

a second unit coupled to the variable speed bus, the second unit having a second rate of requests to access the variable speed bus; and

an arbitration and bus clock control unit to monitor the first access request rate from the first unit and the second access request from the second unit, and to determine a second clock frequency for the variable speed bus based on the first access rate or the second access request rate, the arbitration and bus clock control unit being modified to track a rate of request of the first and second units to access the variable speed bus, the arbitration and bus clock control unit being further modified to recognize when there are no incoming requests and a percentage of arbitration slots that are being used, and to instruct a clock throttling logic to adjust a clock frequency associated with the variable speed bus according to bandwidth requirements of the first and second units based on the rate of request, wherein the adjusting of the clock frequency includes lowering the clock frequency to a lowest level necessary in accordance with the recognition of no incoming requests and the percentage of the arbitration slots being used and further in accordance with a historical average utilization including statistical data relating to sustained bandwidth needs such that the clock frequency of the variable speed bus is automatically adjusted depending on one or more of the rate of request, the percentage of arbitration slots being used, and the historical average utilization relating to the first and second units.

2. The apparatus of claim 1, wherein the first unit comprises a processor unit.

3. The apparatus of claim 1, wherein the second unit comprises a video processor unit.

4. The apparatus of claim 1, wherein the first unit comprises a hard disk drive controller unit.

5. The apparatus of claim 1, wherein the second unit comprises an isochronous data transfer unit.

6. The apparatus of claim 5, wherein the isochronous data transfer unit comprises a 1394 controller unit.

7. The apparatus of claim 5, wherein the isochronous data transfer unit comprises a USB controller unit.

8. The method of claim 1, wherein the first unit comprises a processor unit.

9. The method of claim 1, wherein the second unit comprises a video processor unit.

10. The method of claim 1, wherein the first unit comprises a hard disk drive controller unit.

11. The method of claim 1, wherein the second unit comprises an isochronous data transfer unit.

12. A system, comprising:

a device coupled to a variable speed bus, the device having a rate of request to access the variable speed bus; and

an arbitration and bus clock control unit to monitor the rate of request, and to determine a clock frequency associated with the variable speed bus based on the rate of request, the arbitration and bus clock control unit being modified to track the rate of request to access the variable speed bus, the arbitration and bus clock control unit being further modified to recognize when there are no incoming requests and a percentage of arbitration slots that are being used, and to instruct a clock throttling logic to adjust the clock frequency associated with the variable speed bus based on the rate of request to access the variable speed bus from the device, wherein the adjusting of the clock frequency includes lowering the clock frequency to a lowest level necessary in accordance with the recognition of no incoming requests and the percentage of the arbitration slots being used and further in accordance with a historical average utilization including statistical data relating to sustained bandwidth needs such that the clock frequency of the variable speed bus is automatically adjusted depending on one or more of the rate of request, the percentage of arbitration slots being used, and the historical average utilization relating to the first and second units.

13. The system of claim 12, wherein the device coupled to the variable speed bus comprises a processor.

14. The system of claim 12, wherein the device coupled to the variable speed bus comprises a video processor.

15. The system of claim 12, wherein the device coupled to the variable speed bus comprises a hard disk drive controller.

16. The system of claim 12, wherein the device coupled to the variable speed bus comprises an isochronous data transfer controller.

17. The system of claim 16, wherein the isochronous data transfer controller comprises a 1394 controller.

18. The system of claim 16, wherein the isochronous data transfer controller comprises a USB controller.

19. The system of claim 12, wherein the arbitration and bus clock control unit determines the second clock frequency based on a first bandwidth requirement from the first unit and a second bandwidth requirement from the second unit, the first bandwidth requirement derived from the first rate of request to access the variable speed bus from the first unit, the second bandwidth requirement derived from the second rate of request to access the variable speed bus from the second unit.

20. The system of claim 12, wherein the variable speed bus, the first unit, the second unit, the clock throttling logic and the arbitration and clock control unit are located on a single semiconductor die.

21. A method comprising:

accessing the variable speed bus by the first unit having a first rate of requests, the first unit coupled to the variable speed bus;

accessing the variable speed bus by the second unit having a second rate of requests, the second unit coupled to the variable speed bus; and

monitoring, by an arbitration and bus clock control unit, the first access request rate from the first unit and the second access request from the second unit, and to determine a second clock frequency for the variable speed bus based on the first access rate or the second access request rate, the arbitration and bus clock control unit being modified to track a rate of request of the first and second units to access the variable speed bus, the arbitration and bus clock control unit being further modified to recognize when there are no incoming requests and a percentage of arbitration slots that are being used, and to instruct a clock throttling logic to adjust a clock frequency associated with the variable speed bus according to bandwidth requirements of the first and second units based on the rate of request, wherein the adjusting of the clock frequency includes lowering the clock frequency to a lowest level necessary in accordance with the recognition of no incoming requests and the percentage of the arbitration slots being used and further in accordance with a historical average utilization including statistical data relating to sustained bandwidth needs such that the clock frequency of the variable speed bus is automatically adjusted depending on one or more of the rate of request, the percentage of arbitration slots being used, and the historical average utilization relating to the first and second units.