Context save and restore with a stack-based memory structure

• US 7,606,977 B2
• Filed: 07/25/2005
• Issued: 10/20/2009
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Lesot, Jean-Philippe
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US11/188,411
• Publication Number:
  US 20060026357A1
• Time in Patent Office: 1,548 Days
• Field of Search: 711/100, 711/117, 711/118, 711/119, 711/129, 711/154, 711/173, 711/132
• US Class Current: 711/132
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a first portion and a second portion, and wherein only one of the first or second portions is active at a time, the non-active portion being unusable. When the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion. Upon a thread switch from a first thread to a second thread, only one of the first or second portions is cleaned to the external memory if one of the first or second portions does not contain valid data.

Claims

1. A multi-threaded processor adapted to couple to external memory, comprising:

a controller;

data storage operated by said controller, said data storage comprises a first portion and a second portion, and wherein only one of said first or second portions is active at a time, the non-active portion being unusable;

wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion; and

wherein, upon a thread switch from a first thread to a second thread, only one of said first or second portions is cleaned, to the external memory if one of said first or second portions does not contain valid data.

2. The processor of claim 1 wherein, when said first and second portions of the data storage are used to store local variables associated with a stack-based programming language.

3. The processor of claim 1 wherein data contents of the first or second portion that is cleaned to the external memory are copied to a corresponding portion of a memory-mapped version of the data storage.

4. The processor of claim 1 wherein the data storage is mapped to a corresponding area of the external memory.

5. The processor of claim 4 wherein the data storage is re-mapped to a different area of the external memory before the first or second portion that is cleaned to the external memory is actually cleaned.

6. The processor of claim 1 wherein said data storage comprises cache memory.

7. The processor of claim 1 wherein if both portions of the data storage comprise valid data, then both portions are cleaned to the external memory upon a thread switch.

8. The processor of claim 7 wherein the data storage is re-mapped to a different area of the external memory before cleaning both portions or after cleaning one portion but before cleaning the other portion.

9. The processor of claim 1 wherein, upon a subsequent switch back to the first thread, the cleaned data is brought back into the data storage from the external memory.

10. A system, comprising:

a communications transceiver;

a controller;

data storage operated by said controller, said data storage comprises a first portion and a second portion, and wherein only one of said first or second portions is active at a time, the non-active portion being unusable;

wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion; and

wherein, upon a thread switch from a first thread to a second thread, only one of said first or second portions is cleaned to the external memory if one of said first or second portions does not contain valid data.

11. The system of claim 10 wherein, when said first and second portions of the data storage are used to store local variables associated with a stack-based programming language.

12. The system of claim 10 wherein data contents of the first or second portion that is cleaned to the external memory are copied to a corresponding portion of a memory-mapped version of the data storage.

13. The system of claim 10 wherein the data storage is mapped to a corresponding area of the external memory.

14. The system of claim 13 wherein the data storage is re-mapped to a different area of the external memory before the first or second portion that is cleaned to the external memory is actually cleaned.

15. The system of claim 10 wherein said data storage comprises cache memory.

16. The system of claim 10 wherein if both portions of the data storage comprise valid data, then both portions are cleaned to the external memory upon a thread switch.

17. The system of claim 16 wherein the data storage is re-mapped to a different area of the external memory before cleaning both portions or after cleaning one portion but before cleaning the other portion.

18. The system of claim 10 wherein, upon a subsequent switch back to the first thread, the cleaned data is brought back into the data storage from the external memory.

19. The system of claim 10 wherein the system comprises a cellular telephone.

20. A method, comprising:

using only a first portion of a cache memory data array to store local variables until said first portion has insufficient capacity for storing additional local variables, said cache memory data array comprising the first portion and a second portion;

once the first portion has insufficient capacity for storing additional local variables, using only the second portion of the cache memory data to store said additional local variables and not using the first portion;

when the second portion has insufficient capacity for storing additional local variables, copying the local variables from only the first portion to external memory;

switching from a first thread to a second thread; and

upon switching to the second thread, cleaning only one of said first or second portions to the external memory if one of said first or second portions does not contain valid data.