Augmented instruction set for proactive synchronization within a computer system

• US 7,606,985 B2
• Filed: 08/23/2006
• Issued: 10/20/2009
• Est. Priority Date: 08/23/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Alsup, Mitchell
• Primary Examiner(s): Kim; Matt
• Assistant Examiner(s): SCHNEE, HAL W
• Application Number:
  US11/508,492
• Publication Number:
  US 20070050560A1
• Time in Patent Office: 1,154 Days
• Field of Search: 711/152, 711/155, 711/163, 711/150, 711/147
• US Class Current: 711/152
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of memory resources. The set of instructions includes an ACQUIRE instruction. In addition, the method may include storing addresses referenced by the set of instructions within a buffer. Further, the method may include sending the addresses referenced by the set of instructions, as a set, to be compared to other addresses to which exclusive access to memory addresses has been granted in response to execution of the ACQUIRE instruction.

Claims

1. A method comprising:

a processor that implements an x86 architecture executing a set of instructions comprising a critical code section to request exclusive access to a plurality of memory resources using a plurality of memory mov instructions each including an x86 lock instruction prefix, and each specifying a memory address of a respective one of the plurality of memory resources, wherein the set of instructions includes an acquire instruction that comes after the mov instructions in program order;

storing each memory address referenced by the set of instructions within a processor buffer;

wherein, in response to execution of the acquire instruction, sending each memory address stored within the processor buffer, as a set, to be compared to other addresses to which exclusive access has been granted.

2. The method as recited in claim 1, further comprising returning a count value to a register of the processor specified in the acquire instruction in response to execution of the acquire instruction.

3. The method as recited in claim 2, further comprising modifying a particular flag within a condition code register of the processor in response to receiving a non-zero count value.

4. The method as recited in claim 3, further comprising causing a failure of the acquire instruction in response to determining that the particular flag has been set to zero.

5. The method as recited in claim 4, wherein the particular flag comprises a zero flag of the condition code register of the processor.

6. The method as recited in claim 2, wherein the count value is indicative of a number of requestors contending for any of the addresses referenced in the set of instructions.

7. The method as recited in claim 1, further comprising the processor executing each of the mov instructions having the x86 lock instruction prefix causes data stored at a corresponding memory address that is referenced in the set of instructions to be loaded to a register within the processor.

8. The method as recited in claim 1, wherein the set of instructions further comprises a release instruction, wherein in response to execution of the release instruction, releasing the addresses referenced in the set of instructions for use by other requestors.

9. The method as recited in claim 1, wherein the set of instructions further comprises a release instruction, wherein in response to execution of the release instruction, all of the modified data from an atomic phase of the critical code section in which data is modified atomically becomes visible to other processors substantially simultaneously.

10. The method as recited in claim 1, wherein the addresses stored within the buffer comprise physical addresses.

11. A processor that implements an x86 architecture coupled to one or more memories and to one or more additional processors, the processor comprising:

an execution pipeline configured to execute a set of instructions comprising a critical code section to request exclusive access to a given memory resources, wherein the critical code section includes a plurality of memory reference mov instructions, each including an x86 lock instruction prefix, and each specifying a memory address of the memory, wherein the set of instructions further includes an acquire instruction that comes after the mov instructions in program order;

an interface unit including a buffer, wherein the interface unit is coupled to the instruction pipeline and configured to store each memory address referenced by the set of instructions within the buffer;

wherein, in response to execution of the acquire instruction, the interface unit is further configured to send each memory address, as a set, to be compared to other addresses to which exclusive access has been granted.

12. The processor as recited in claim 11, wherein in response to execution of the acquire instruction, the interface unit is further configured to return a count value to a register of the processor specified in the acquire instruction.

13. The processor as recited in claim 12, wherein the interface unit is configured to modify a particular flag within a condition code register of the processor in response to receiving a non-zero count value.

14. The processor as recited in claim 13, wherein the execution pipeline is configured to fail the acquire instruction in response to determining the particular flag has been set to zero.

15. The processor as recited in claim 14, wherein the particular flag comprises a zero flag of the condition code register of the processor.

16. The processor as recited in claim 12, wherein the count value is indicative of a number of requestors contending for any of the addresses referenced in the set of instructions.

17. The processor as recited in claim 11, wherein execution of each of the mov instructions having the x86 lock instruction prefix causes data stored at a corresponding memory address that is referenced in the set of instructions to be loaded to a register within the processor.

18. The processor as recited in claim 11, wherein the set of instructions further comprises a release instruction, wherein upon execution of the release instruction, the interface unit is configured to cause the addresses referenced in the set of instructions to be released for use by other requestors by sending a completion message.

19. The processor as recited in claim 11, wherein the set of instructions further comprises a release instruction, wherein upon execution of the release instruction, all of the modified data from an atomic phase of the critical code section in which data is modified atomically becomes visible to other processors substantially simultaneously.

20. The processor as recited in claim 11, wherein the addresses stored within the buffer comprise physical addresses.

21. A computer readable storage medium including a set of program instructions comprising a critical code section that is executable by a processor that implements an x86 architecture to:

request exclusive access to a plurality of memory resources using a plurality of memory mov instructions each including an x86 lock instruction prefix, and each specifying a memory address of a respective one of the plurality of memory resources, wherein the set of program instructions includes an acquire instruction that comes after the mov instructions in program order;

store each memory address referenced by the set of program instructions within a buffer of the processor;

send each memory address stored within the processor buffer, as a set, to be compared to other addresses to which exclusive access has been granted in response to execution of the acquire instruction;

wherein, in response to execution of the acquire instruction, sending each memory address stored within the processor buffer, as a set, to be compared to other addresses to which exclusive access been granted.

22. The computer readable storage medium as recited in claim 21, wherein the set of program instructions are further executable by the processor to cause a count value to be returned to a register of the processor specified in the acquire instruction in response to execution of the acquire instruction.

23. The computer readable storage medium as recited in claim 22, wherein the set of program instructions are further executable by the processor to cause a particular flag within a condition code register of the processor to be set to zero in response to receiving a non-zero count value.

24. The computer readable storage medium as recited in claim 23, wherein the set of program instructions are further executable by the processor to fail the acquire instruction in response to determining the particular flag has been set to zero.

25. The computer readable storage medium as recited in claim 22, wherein the count value is indicative of a number of requestors contending for any of the addresses referenced by the set of instructions.

26. The computer readable storage medium as recited in claim 21, wherein in response to executing each of the mov instructions having the x86 lock instruction prefix instructions, data stored at a corresponding memory address referenced in the set of program instructions is loaded to a register within the processor.