Systems and methods for CPU repair

• US 7,607,038 B2
• Filed: 02/17/2006
• Issued: 10/20/2009
• Est. Priority Date: 02/18/2005
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kuntz, Guy, Sedmak, Michael, Pomaranski, Ken, Barlow, Jeff, Brauch, Jeff, Joyal, Lacey, Hack, Stephen, Calkin, Howard, Gratias, Raymond
• Primary Examiner(s): Beausoliel; Robert
• Assistant Examiner(s): Manoskey; Joseph D
• Application Number:
  US11/357,384
• Publication Number:
  US 20060248392A1
• Time in Patent Office: 1,341 Days
• Field of Search: 714/3, 714/6, 714/7, 714/8, 714/42, 714/710, 714/711, 714/10
• US Class Current: 714/6.32
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/78 using programmable devices

Abstract

In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.

Claims

1. A method for repairing a faulty cache element associated with a CPU in a computer system, said method comprising the steps of:

determining that a cache element is faulty;

storing repair information, a CPU serial number, and cache configuration in a non-volatile memory;

rebooting said computer system;

swapping in a spare cache element for said faulty cache element during system reboot;

reading a CPU serial number from said CPU;

comparing the read CPU serial number with the stored CPU serial number; and

clearing said repair information and said cache configuration from said non-volatile memory if the stored CPU serial number does not match the read CPU serial number.

2. The method of claim 1, further comprising the steps of:

reading burned cache fuse data from said CPU; and

storing said burned cache data into said non-volatile memory.

3. The method of claim 1, further comprising the steps of:

reading burned cache fuse data from said CPU if the stored CPU serial number matches the read CPU serial number;

storing said read burned cache fuse data into said non-volatile memory; and

reading said cache configuration from said non-volatile memory.

4. The method of claim 1 wherein said non-volatile memory is an EEPROM.

5. A method for repairing a processor, said method comprising the steps of:

determining that an allocated cache element associated with said processor is faulty and in need of repair;

storing repair information into a non-volatile memory;

storing a processor serial number;

swapping in a spare cache element for said faulty allocated cache element during system reboot;

reading a processor serial number from said processor;

comparing the read processor serial number with the stored processor serial number; and

clearing said repair information and said cache configuration from said non-volatile memory if the stored processor serial number does not match the read processor serial number.

6. The method of claim 5, further comprising the steps of:

monitoring for a cache error while an operating system is running; and

recording cache error information in said non-volatile memory; and

generating said system reboot.

7. The method of claim 5, further comprising the step of:

determining whether said spare cache element is available if said currently-used cache element is determined to be faulty during said system reboot.

8. The method of claim 5, further comprising the step of:

reporting actions taken and updating cache configuration in said non-volatile memory.

9. The method of claim 5, wherein said non-volatile memory is an EEPROM.

10. A CPU cache element management system comprising:

a CPU having a currently-used cache element and a spare cache element;

a cache management logic operable to;

determine whether currently-used cache elements are faulty and store a CPU serial number;

swap in said spare cache element for said currently-used cache element during a system reboot;

read a CPU serial number from said CPU; and

compare the read CPU serial number with the stored CPU serial number; and

a non-volatile memory operable to store cache configuration, repair information and CPU serial numbers, wherein said repair information and said cache configuration are removable from said non-volatile memory if the stored CPU serial number does not match the read CPU serial number.

11. The CPU cache element management system of claim 10, wherein said cache management logic is further operable to monitor cache errors and record cache error information in said non-volatile memory.

12. The CPU cache management system of claim 10, wherein said cache management logic is further operable to determine, during system reboot, whether said spare cache element is available if said currently-used cache element is determined to be faulty.

13. The CPU cache management system of claim 10, wherein said cache management logic is further operable to schedule said system reboot.

14. The CPU cache management system of claim 10, wherein said cache management logic is further operable to report actions taken and update cache configuration in said non-volatile memory.

15. The CPU cache management system of claim 10, wherein said non-volatile memory is an EEPROM.

16. A method for managing a computer system having an operating system comprising the steps of:

monitoring a cache element on a CPU for a cache error;

recording cache error information upon occurrence of said cache error in a non-volatile memory;

determining whether said cache element is faulty based on said cache error information;

storing cache element repair information and CPU serial number in said non-volatile memory;

generating a system reboot;

reading a CPU serial number from said CPU;

comparing the read CPU serial number with the stored CPU serial number;

reading burned cache fuse data from said CPU if the stored CPU serial number does not match the read CPU serial number;

storing said read burned cache fuse data into said non-volatile memory if the stored CPU serial number does not match the read CPU serial number;

reading said cache configuration and from said non-volatile memory;

determining if a spare cache element is available if said cache element is faulty during said system reboot;

swapping in said spare cache element if said spare cache element is available and said cache element is faculty during said system reboot; and

updating cache configuration in said non-volatile memory.

17. The method of claim 16, wherein said cache element is determined to be faulty if a total number of errors occurring from said cache element exceeds a predetermined threshold.

18. The method of claim 17, wherein said predetermined threshold is based on a total number of errors occurring from said cache element over a predetermined time period.

19. The method of claim 16, wherein said monitoring step is performed by cache management logic within said operating system.

20. The method of claim 16, further comprising the step of:

de-allocating said at least one CPU if said at least one spare cache element is not available.

21. The method of claim 20, further comprising the steps of:

determining whether a spare CPU is available; and

swapping in said spare CPU for said de-allocated CPU if said spare CPU is available.

22. The method of claim 16, wherein said non-volatile memory is an EEPROM.

23. A processor comprising:

a plurality of first memory portions;

a plurality of second memory portions;

a non-volatile memory on said processor;

logic for determining whether a first memory portion is faulty;

logic for storing memory portion error information, repair information, a processor serial number, and configuration in said non-volatile memory; and

logic for replacing the faulty first memory portion with a second memory portion during a system reboot;

logic for reading a processor serial number from said processor;

logic for comparing the read processor serial number with the stored processor serial number; and

logic for clearing said repair information and said cache configuration from said non-volatile memory if the stored processor serial number does not match the read processor serial number.

24. The processor of claim 23 wherein the logic for determining whether a first memory portion is faulty comprises logic for monitoring errors associated the first memory portion.

25. The processor of claim 23 wherein the logic for determining whether a first memory portion is faulty comprises logic for comparing a number of errors associated with the first memory portion to a threshold value.

26. The processor of claim 23 wherein the logic for replacing the faulty first memory portion with a second memory portion comprises logic for determining if a second memory portion is available for use in the replacement.

27. The processor of claim 23 wherein the logic for replacing the faulty first memory portion with a second memory portion comprises logic for de-allocating the processor if a second memory portion is not available for use in the replacement.

28. The processor of claim 23, wherein said non-volatile memory is an EEPROM.

29. A processor comprising:

a first cache means configured for high-speed information storage and retrieval from the processor;

a second cache means for high-speed information storage and retrieval;

a non-volatile memory on said processor;

means for determining whether any portion of the first cache means configured for high-speed information storage is faulty;

means for storing cache error information, repair information, a processor serial number, and cache configuration in said non-volatile memory; and

means for replacing the faulty portion of the first cache means with at least a portion of the second cache means for high-speed information storage and retrieval during a system reboot;

means for reading a serial number from said processor;

means for comparing the read processor serial number with the stored processor serial number; and

means for clearing repair information and said cache configuration from said non-volatile memory if the stored processor serial number does not match the read processor serial number.

30. The processor of claim 29, wherein the means for determining comprises means for monitoring errors associated the first cache means.

31. The processor of claim 29, wherein the means for determining comprises means for comparing a number of errors associated with the first cache means to a threshold value.

32. The processor of claim 29, wherein the means for replacing comprises means for determining if any portion of the second cache means is available for use in the replacement.

33. The processor of claim 29, wherein the means for replacing comprises means for de-allocating the processor if no portion of the second cache means is available for use in the replacement.

34. The processor of claim 29, wherein said non-volatile memory is an EEPROM.