High performance stress-enhance MOSFET and method of manufacture

• US 7,608,489 B2
• Filed: 04/28/2006
• Issued: 10/27/2009
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Donaton, Ricardo A., Rim, Kern, Henson, William K., Chidambarrao, Dureseti
• Primary Examiner(s): Mandala; Victor
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US11/380,689
• Publication Number:
  US 20070254423A1
• Time in Patent Office: 1,278 Days
• Field of Search: 257/204, 257/206, 257/E29.049, 257/E29.299, 257/213, 257/E21.615, 257/E21.618, 257/E21.634, 438/153, 438/188, 438/199, 438/218, 438/229, 438/142, 438/154, 438/221, 438/222, 438/694, 438/938
• US Class Current: 438/142
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

Claims

1. A method of manufacturing a semiconductor structure:

forming, simultaneously, a layered structure with an underlying stress inducing material, in a p-type field-effect-transistor (PFET) channel region and a n-type field-effect-transistor (NFET) channel region;

protecting the NFET channel region while forming a layer over the underlying stress inducing material of the PFET channel region; and

etching an island in the NFET channel region and the PFET channel region, creating a higher resultant stress component in the NFET channel region; and

forming a stress inducing material in the etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region.

2. The method of claim 1, wherein the layered structure with an underlying stress inducing material includes a top layer of Si and an underlying layer of SiGe, wherein the top layer of Si is of a different thickness respective to the NFET or PFET channel regions.

3. The method of claim 1, wherein the PFET channel region is thicker than the NFET channel region.

4. The method of claim 1, wherein the PFET channel region has a top layer thicker than the NFET channel region.

5. The method of claim 1, wherein the layered structure with an underlying stress inducing material includes a top layer of Si and an underlying layer of SiGe, wherein the top layer of Si in the PFET channel region is thicker than the top layer of Si in the NFET channel region.

6. The method of claim 5, wherein the germanium content of the SiGe is approximate from 20% and 30%.

7. The method of claim 5, wherein a thickness of the top layer of Si in the PFET channel region is approximately 400 Å

.

8. The method of claim 1, wherein a thickness of an Si layer in the PFET channel region substantially reduces tensile stress in the PFET channel region prior to the forming of the stress inducing material in etched portions of the PFET channel region.

9. The method of claim 8, wherein the stress inducing material in etched portions of the PFET channel region create compressive forces in the PFET channel region.

10. The method of claim 1, wherein the etching and forming steps of the PFET channel region are provided while the NFET channel region is protected.