Fabrication method of trenched power MOSFET with low gate impedance

• US 7,608,511 B1
• Filed: 11/06/2008
• Issued: 10/27/2009
• Est. Priority Date: 11/06/2008
• Status: Active Grant

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Hsu, Hsiu Wen
• Primary Examiner(s): Pham; Thanhha
• Application Number:
  US12/289,860
• Time in Patent Office: 355 Days
• Field of Search: 438/259, 438270-271, 438/589, 257/E21.655
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A fabrication method of a trenched power MOSFET with low gate impedance is provided. The fabrication method comprising the steps of: forming a plurality of trenches in an epitaxial layer; forming a gate oxide layer on the epitaxial layer; forming a plurality of polysilicon gates in the trenches; implanting dopants with a first conductivity type into the epitaxial layer; driving-in the dopants in an oxygen-free environment to form a body; implanting dopants with a second conductivity type into the body; driving-in the dopants with the second conductivity type in an oxygen-free environment to form a plurality of source regions; forming self alignment silicide on the polysilicon gates by using the gate oxide layer as a mask; depositing a dielectric layer on the epitaxial layer and forming a window therein exposing the source regions; and forming a heavily doped region of the first conductivity type in the body beneath the window.

Claims

1. A fabrication method of a trenched power MOSFET comprising steps of:

providing a substrate and forming an epitaxial layer thereon;

forming a plurality of gate trenches in the epitaxial layer;

forming a gate oxide layer on an exposed surface of the epitaxial layer;

forming a plurality of polysilicon gates in the gate trenches respectively;

implanting dopants with a first conductivity type into the epitaxial layer below the gate oxide layer;

driving-in the dopants with the first conductivity type in an oxygen-free environment to form a body below the gate oxide layer;

implanting dopants with a second conductivity type into the body below the gate oxide layer;

driving-in the dopants with the second conductivity type in an oxygen-free environment to form a plurality of source regions in the body;

forming self alignment silicide (salicide) on exposed surfaces of the polysilicon gates by using the gate oxide layer as a mask;

depositing a dielectric layer covering the epitaxial layer and the polysilicon gates and forming a contact window to expose the source region and part of the body; and

forming a heavily-doped region with the first conductivity type into the body beneath the contact window.

2. The fabrication method of claim 1, wherein the oxygen-free environment to form the body and the oxygen-free environment to form the plurality of the source regions are substantially pure-nitrogen environments.

3. The fabrication method of claim 1, wherein the oxygen-free environment to form the body and the oxygen-free environment to form the plurality of the source regions are vacuum environments.

4. The fabrication method of claim 1, wherein the oxygen-free environment to form the body and the oxygen-free environment to form the plurality of the source regions are substantially inert gas environments.

5. The fabrication method of claim 1, wherein the step of forming the self alignment silicide comprising the steps of:

forming a metal layer covering the gate oxide layer and the polysilicon gates; and

applying a thermal processing to have the metal layer react with the polysilicon gates to form self alignment silicide.

6. The fabrication method of claim 5, wherein the thermal processing is a rapid thermal processing.

7. The fabrication method of claim 5, wherein the metal layer is a titanium metal layer.

8. The fabrication method of claim 5, wherein after the step of forming the metal layer, further comprising a step of forming a titanium nitride layer covering the metal layer.

9. The fabrication method of claim 1, wherein the drive-in step of the dopants with the first conductivity type is performed at 1000°

C.˜

1150°

C. for about 20˜

50 minutes.

10. The fabrication method of claim 1, wherein the drive-in step of the dopants with the second conductivity type is performed at 850°

C.˜

950°

C. for about 15˜

30 minutes.

11. The fabrication method of claim 1, wherein before the step of implanting the dopants with the second conductivity type into the body, further comprising a step of forming a patterned photoresistant layer on the gate oxide layer to define locations of the source regions.

12. The fabrication method of claim 1, wherein the dopants with the second conductivity type are implanted in the body below the gate oxide layer by performing blank implant.

13. The fabrication method of claim 12, wherein in the step of forming the contact window, part of the source regions beneath the contact window is removed simultaneously to expose the body under the source regions.

14. The fabrication method of claim 1, wherein after the step of forming the source regions, upper surfaces of the polysilicon gates are substantially remained exposed.