Bridge resistance random access memory device with a singular contact structure

• US 7,608,848 B2
• Filed: 05/09/2006
• Issued: 10/27/2009
• Est. Priority Date: 05/09/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Ho, ChiaHua, Hsieh, Kuang Yeu
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): Budd; Paul A
• Application Number:
  US11/382,422
• Publication Number:
  US 20070262388A1
• Time in Patent Office: 1,267 Days
• Field of Search: 257 1- 4, 257/E29.17
• US Class Current: 257/3
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.

Claims

1. A memory device, comprising:

a first electrode, electrically connected to an access device, including an annular portion with an interior area, the first electrode having an edge surface on the annular portion;

a second electrode, electrically connected to a bit line, spaced apart from the first electrode and situated within the interior area, the second electrode having an edge surface;

an insulating material separating the first and second electrodes; and

a memory material in contact with the edge surface of the first electrode and the edge surface of the second electrode.

2. The device of claim 1, wherein the memory material comprises a bridge of programmable resistance memory material that extends horizontally across and in contact with the first electrode, the insulating material and the second electrode.

3. The device of claim 2, further comprising a spacer disposed over the programmable resistance memory material that protects the programmable resistance memory material from a dielectric breakthrough.

4. The device of claim 3, wherein the bit line comprises a conductive material that is deposited over the spacer, the bit line in contact with the second electrode.

5. The device of claim 1, further comprising a via formed on a top surface of the second electrode;

the bit line including a conductive material deposited into the via.

6. The device of claim 2, further comprising a hard mask formed over the programmable resistance memory material.

7. The device of claim 1, wherein the first electrode extends through a contact via to a contact surface, and includes an annular structure lining the contact via and a conductive material inside the annular structure and in contact with the contact surface and filling up a portion of the contact via, said annular portion of the first electrode extending above the conductive material.

8. The device of claim 1, wherein the second electrode comprises W, TiN or TaN.

9. The device of claim 1, wherein the access device comprises a transistor.

10. The device of claim 1, wherein the first and second electrodes are disposed within a contact structure.

11. The device of claim 2, wherein the bridge of programmable resistance memory material comprises a structure having a rectangular top surface and a rectangular bottom surface, the bottom surface contacting the edges surfaces of the first and second electrodes.

12. The device of claim 2, wherein the programmable resistance memory material comprises a chalcogenide.

13. The device of claim 2, wherein the programmable resistance memory material bridge has at least two solid phases which are reversibly inducible by a current.

14. The device of claim 2, wherein the programmable resistance material has at least two solid phases which include a generally amorphous phase and a generally crystalline phase.

15. The device of claim 2, wherein the programmable resistance memory material bridge comprises GeSbTe.

16. The device of claim 2, wherein the programmable resistance memory material comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, or Au.

17. The device of claim 2, wherein the programmable resistance memory material comprises a colossal magnetoresistance material.

18. The device of claim 2, wherein the programmable resistance memory material comprises a two-element compound.