Accurate scan-mode voltage detection circuit

• US 7,609,049 B1
• Filed: 05/28/2008
• Issued: 10/27/2009
• Est. Priority Date: 05/28/2008
• Status: Expired due to Fees

• Current Assignee: Vimicro Corporation
• Original Assignee: Vimicro Corporation
• Inventors: Zhao, Wang, Yin, Hang, Tian, Wenbo
• Primary Examiner(s): NGUYEN, HOAI AN D
• Application Number:
  US12/127,824
• Time in Patent Office: 517 Days
• Field of Search: 324/76.11, 324/522, 324/71.1, 324/713, 324/429, 361/30, 361/79, 361/86, 361/56, 361/91.1, 340/636.12, 340/636.15, 327/78, 327/81, 330/255, 330/288
• US Class Current: 324/76.11
• CPC Class Codes: G01R 19/16542 for batteries charge condition monitoring in G01R31/36

Abstract

A scan mode is used in a voltage detection circuit. An oscillator in the circuit is always on and a system including the voltage detection circuit detects various abnormal conditions, such as overcharging, overdischarging and overcurrent one by one for some clocks. To reduce the power consumption, the voltage detection circuit is turned on only once for several clocks. The on-time is very short and lasts about only one tenth of a clock cycle time. In other times, the voltage detection circuit is turned off to save power consumption.

Claims

1. A voltage detection circuit comprising:

first and second transistors, gates of the first and second transistors coupled to each other, sources of the first and second transistors coupled to each other, the gate of the first transistor coupled to a drain of the first transistor;

a first switch circuit configured for selectively coupling a positive voltage to the sources of the first and second transistors;

first and second bipolar transistors, bases of the first and second bipolar transistors coupled to each other, a collector of the first bipolar transistor coupled to the drain of the first transistor, a collector of the second bipolar transistor coupled to a drain of the second transistor;

a pair of resistors coupled in series between an emitter of the first bipolar transistor and a negative power, an emitter of the second bipolar transistor coupled to an intermediate node between the pair of resistors, wherein the base of the first bipolar transistor is regarded as a detection voltage input, and the collector of the second bipolar transistor is regarded as a detection result output.

2. The voltage detection circuit according to claim 1, further comprising a voltage divider, wherein

one terminal of the voltage divider is coupled to the positive power by a second switch circuit in series, the other terminal of the voltage divider is coupled to the negative power, and

the voltage divider is configured for providing a divided voltage to the detection voltage input, and the second switch circuit is configured for selectively coupling the positive power to the voltage divider.

3. The voltage detection circuit according to claim 2, further comprising an amplifier circuit including a bias current source, a gain amplifying transistor, and third and fourth transistors, wherein

gates of the third and fourth transistors are coupled with each other, sources of the third and fourth transistors are coupled to the negative power respectively, and the gate of the third transistor is coupled to a drain of the third transistor by a third switch circuit in series, the third switch circuit is configured for selectively coupling the gate of the third transistor to the drain of the third transistor;

an input terminal of the bias current source is coupled to the positive power, an output terminal of the bias current source is coupled to the drain of the third transistor by a fourth switch circuit in series, the fourth switch circuit is configured for selectively coupling the drain of the third transistor to the output terminal of the bias current source;

a gate of the gain amplifying transistor is coupled to the detection result output, a source of the gain amplifying transistor is coupled to the sources of the first and second transistors, and a drain of the gain amplifying transistor is coupled to a drain of the fourth transistor; and

wherein the drain of the gain amplifying transistor outputs an amplified detection result.

4. The voltage detection circuit according to claim 3, further comprising an inverter serving as a shaping circuit, wherein

an input terminal of the inverter is coupled to the drain of the gain amplifying transistor, an output terminal of the inverter output a final detection result;

and

a fifth switch circuit is coupled between the input terminal of the inverter and the negative power and is configured for selectively coupling the input terminal of the inverter to the negative power.

5. The voltage detection circuit according to claim 3, wherein the first and second transistors are p-type MOS transistor, the third and fourth transistors are n-type MOS transistors, and the gain amplifying transistor is a p-type MOS transistor.

6. The voltage detection circuit according to claim 1, wherein an area of the emitter of the first bipolar transistor is larger than that of the emitter of the second bipolar transistor.

7. The voltage detection circuit according to claim 4, wherein each of the first, second and fourth switch circuits is a p-type MOS transistor, and each of the third and fifth switch circuits is a n-type MOS transistor, wherein

gates of the first, second, fourth and fifth switch circuits are connected to an enable control terminal;

a gate of the third switch circuit is connected to the enable control terminal by an inverter in series.

8. The voltage detection circuit according to claim 1, further comprising a hysteresis circuit comprising a first hysteresis transistor and a second hysteresis transistor, wherein

a gate of the first hysteresis transistor is connected to the gate of the first transistor, a source of the first hysteresis transistor is connected to the source of the first transistor;

a source of the second hysteresis transistor is connected to a drain of the first hysteresis transistor, a drain of the second hysteresis transistor is connected to the drain of the first transistor; and

a gate of the second hysteresis transistor is configured for receiving a state signal which is obtained according to a detection result from the detection result output.

9. A voltage detection circuit comprising:

a voltage divider coupled between a positive terminal and a negative terminal of a battery and configured for dividing a battery voltage and providing a divided voltage of the battery voltage;

a voltage comparator coupled between the positive terminal and the negative terminal of the battery and configured for comparing the divided voltage from the voltage divider with a reference voltage formed therein and outputting a comparative result;

an output control circuit coupled between the positive terminal and the negative terminal of the battery and configured for amplifying and shaping the comparative result to form a voltage detection result; and

an enable circuit configured for receiving an enable signal to switch on current paths from the positive terminal to the negative terminal of the battery of the voltage divider, the voltage comparator and the output control circuit, or receiving a disenable signal to switch off current paths from the positive terminal to the negative terminal of the battery of the voltage divider, the voltage comparator and the output control circuit, wherein the voltage comparator and the output control circuit comprises plural MOS transistors therein, and voltages on gates of the MOS transistors are maintained to be substantially near to normal operation voltages after the current paths from the positive terminal to the negative terminal of the battery of the voltage divider, the voltage comparator and the output control circuit are switched off.

10. The voltage detection circuit according to claim 9, wherein the voltage comparator comprises:

first and second MOS transistors, gates of the first and second MOS transistors coupled with each other, sources of the first and second MOS transistors coupled with each other, the gate of the first MOS transistor coupled to a drain of the first MOS transistor, sources of the first and second MOS transistors coupled to the positive terminal of the battery by a first switch circuit, the first switch circuit configured for selectively coupling the positive terminal of the battery to the sources of the first and second MOS transistors;

first and second bipolar transistors, bases of the first and second bipolar transistors coupled with each other, a collector of the first bipolar transistor coupled to the drain of the first MOS transistor, a collector of the second bipolar transistor coupled to a drain of the second MOS transistor;

a pair of resistors coupled in series between an emitter of the first bipolar transistor and the negative terminal of the battery, an emitter of the second bipolar transistor coupled to an intermediate node between the pair of resistors, wherein the base of the first bipolar transistor is regarded as an divided voltage input of the voltage comparator, and the collector of the second bipolar transistor is regarded as a comparative result output of the voltage comparator.

11. The voltage detection circuit according to claim 10, wherein the output control circuit comprises an amplifying circuit including a bias current source, a gain amplifying MOS transistor, and third and fourth MOS transistors, and wherein

gates of the third and fourth MOS transistors are coupled with each other, sources of the third and fourth MOS transistors are coupled to the negative power respectively, and the gate of the third MOS transistor is coupled to a drain of the third MOS transistor by a third switch circuit in series, the third switch circuit is configured for selectively coupling the gate of the third MOS transistor to the drain of the third MOS transistor;

an input terminal of the bias current source is coupled to the positive terminal of the battery, an output terminal of the bias current source is coupled to the drain of the third MOS transistor by a fourth switch circuit in series, the fourth switch circuit is configured for selectively coupling the drain of the third MOS transistor to the output terminal of the bias current source;

a gate of the gain amplifying MOS transistor is coupled to the comparative result output, a source of the gain amplifying MOS transistor is coupled to the sources of the first and second MOS transistors, and a drain of the gain amplifying MOS transistor is coupled to a drain of the fourth MOS transistor; and

wherein the drain of the gain amplifying MOS transistor outputs an amplified comparative result.

12. The voltage detection circuit according to claim 10, wherein an area of the emitter of the first bipolar transistor is larger than that of the emitter of the second bipolar transistor.

13. The voltage detection circuit according to claim 10, wherein the voltage comparator further comprises a first hysteresis transistor and a second hysteresis transistor, wherein

a gate of the first hysteresis transistor is connected to the gate of the first MOS transistor, a source of the first hysteresis transistor is connected to the source of the MOS first transistor;

a source of the second hysteresis transistor is connected to a drain of the first hysteresis transistor, a drain of the second hysteresis transistor is connected to the drain of the first MOS transistor; and

a gate of the second hysteresis transistor is configured for receiving a state signal which is obtained according to the voltage detection result.