Comparator with low supply current spike and input offset cancellation

• US 7,609,093 B2
• Filed: 08/03/2007
• Issued: 10/27/2009
• Est. Priority Date: 08/03/2007
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Sarig, Erez, Reshef, Raz
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Houston; Adam D
• Application Number:
  US11/833,803
• Publication Number:
  US 20090033370A1
• Time in Patent Office: 816 Days
• Field of Search: 327/65, 327/66, 327/72, 327560-563, 330/252, 330/253
• US Class Current: 327/65
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 2203/45354 the AAC comprising offset means
• CPC Class Codes: H03F 2203/45396 the AAC comprising one or more switches
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Claims

1. A comparator comprising:

a current source that provides a source current to a first node;

a first voltage supply terminal configured to receive a first supply voltage;

a first transistor coupled between the first node and the first voltage supply terminal along a first current path;

a second transistor coupled between the first node and the first voltage supply terminal along a second current path;

a third transistor coupled between the first node and the first voltage supply terminal along a third current path, wherein the first, second and third current paths are separate and parallel current paths between the first node and the first voltage supply terminal;

a first input terminal configured to receive a first differential input signal of the comparator, wherein the first input terminal is coupled to a gate of the first transistor;

a second input terminal configured to receive a second differential input signal of the comparator, wherein the second input terminal is coupled to gates of the second and third transistors;

a first capacitor coupled between the second input terminal and the first voltage supply terminal, wherein the first capacitor applies the second differential input signal to the comparator; and

means for sampling the first differential input signal on the first capacitor.

4. The comparator of claim 1, wherein the first, second and third transistors are PMOS transistors.

5. The comparator of claim 1, further comprising:

a fourth transistor coupling the first transistor to the first voltage supply terminal; and

a fifth transistor coupling the second transistor to the first voltage supply terminal, wherein the fourth and fifth transistors have gates commonly coupled to a drain of the fourth transistor.

6. The comparator of claim 5, further comprising:

an output terminal coupled to a drain of the fifth transistor; and

an output capacitor coupled to the output terminal.

7. The comparator of claim 5, further comprising a sixth transistor coupling the third transistor to the first voltage supply terminal.

2. A comparator comprising:

a current source that provides a source current to a first node;

a first voltage supply terminal configured to receive a first supply voltage;

a first transistor coupled between the first node and the first voltage supply terminal along a first current path;

a second transistor coupled between the first node and the first voltage supply terminal along a second current path;

a third transistor coupled between the first node and the first voltage supply terminal along a third current path, wherein the first, second and third current paths are separate and parallel current paths between the first node and the first voltage supply terminal;

a first input terminal configured to receive a first differential input signal of the comparator, wherein the first input terminal is coupled to a gate of the first transistor;

a second input terminal configured to receive a second differential input signal of the comparator, wherein the second input terminal is coupled to gates of the second and third transistors;

a first capacitor coupled between the second input terminal and the first voltage supply terminal, wherein the first capacitor applies the second differential input signal to the comparator;

an output terminal configured to receive an output signal of the comparator, wherein the output terminal is coupled to a drain of the second transistor; and

a switch coupled between the output terminal and the second input terminal.

3. The comparator of claim 2, further comprising an output capacitor coupled between the output terminal and the first voltage supply terminal.

8. A method of implementing a comparator comprising:

sampling a reference voltage applied to a first input of a differential comparator circuit on a second input of the differential comparator circuit during a first operating phase; and

then

maintaining the reference voltage on the second input of the differential comparator circuit and an input of a current control circuit during a second operating phase, wherein the current control circuit provides a current path in parallel with current paths of the differential comparator circuit; and

applying a ramp voltage to the first input of the differential comparator circuit during the second operating phase.

9. The method of claim 8, wherein the step of sampling the reference voltage comprises coupling the second input of the differential comparator circuit to an output terminal of the differential comparator circuit.

10. The method of claim 9, wherein the step of sampling the reference voltage comprises storing charge on a sampling capacitor coupled to the second input of the differential comparator circuit.

11. The method of claim 8, wherein current flows through the differential comparator circuit and the current control circuit during the first operating phase.

12. The method of claim 11, wherein a current flowing through the differential comparator circuit is about twice a current flowing through the current control circuit during the first operating phase.

13. The method of claim 8, wherein current only flows through the differential comparator circuit during the second operating phase while the ramp voltage is less than the reference voltage.

14. The method of claim 8, wherein current flows through both the differential comparator circuit and the current control circuit during the second operating phase while the ramp voltage is equal to the reference voltage.

15. The method of claim 8, wherein current initially flows through both the differential comparator circuit and the current control circuit during the second operating phase, when the ramp voltage initially exceeds the reference voltage, and wherein current subsequently flows only through the current control circuit during the second operating phase, after the ramp voltage exceeds the reference voltage by a predetermined voltage.

16. The method of claim 8, wherein a current flowing through the differential comparator circuit and the current control circuit during the first operating phase is substantially equal to a current flowing through the differential comparator circuit and the current control circuit during the second operating phase.

17. The method of claim 16, wherein the current flowing through the differential comparator circuit and the current control circuit is substantially constant during the second operating phase.

18. The method of claim 8, wherein a current flowing through the differential comparator circuit and the current control circuit is substantially constant during the second operating phase.