On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip

• US 7,609,100 B2
• Filed: 07/13/2007
• Issued: 10/27/2009
• Est. Priority Date: 03/03/2005
• Status: Expired due to Fees

• Current Assignee: Semiconductor Technology Academic Research Center
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: Nagata, Makoto
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Jager; Ryan C
• Application Number:
  US11/826,271
• Publication Number:
  US 20070262799A1
• Time in Patent Office: 837 Days
• Field of Search: 327/298, 327/299, 327/158, 713/501
• US Class Current: 327/158
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

An on-chip signal waveform measurement apparatus mounted on an IC chip measures signal waveforms at detection points on the IC chip. A reference voltage generator successively generates reference voltages different from each other based on a predetermined timing signal, and Signal probing front-end circuits are mounted to correspond to the detection points, respectively, and each buffer-amplifies a voltage at each detection point, compares the buffer-amplified voltage with each reference voltage, and digitizes a comparison result into a binary digital output signal. A multiplexer time-division-multiplexes the binary digital output signals from the signal probing front-end circuits. A data processing unit calculates a judgment output probability for a detected voltage at each detection point detected by the respective signal probing front-end circuits, by counting a number of times of a predetermined binary value of the multiplexed binary digital output signal.

Claims

1. A sampling timing signal generator for generating an enable timing control signal based on a predetermined system clock signal and a predetermined master clock signal, said sampling timing signal generator comprising:

a replica DLL (Delayed Locked Loop) circuit configured to generate a predetermined reference bias voltage in synchronization with the system clock signal based on the system clock signal, and to output the reference bias voltage; and

a delay signal generator circuit configured to operate for integers n (where “

n”

is an integer equal to or larger than one) and to generate a current obtained by dividing a reference current corresponding to the reference bias voltage by “

n”

, to use the generated divided current for charging an output load capacitance whereby the time for charging the output load capacitance constitutes a desired time delay, the desired time delay being a multiplication product of the number n and an arbitrary delay time to delay the master clock signal by the desired delay time, and to generate a delayed signal as an enable timing control signal,

wherein said replica DLL circuit is configured to generate the reference bias voltage so that the desired delay time is equal to a cycle of the system clock signal, whereby said delay signal generator circuit generates the enable timing control signal.