Low noise active pixel image sensor using a modified reset value

• US 7,609,303 B1
• Filed: 10/12/2005
• Issued: 10/27/2009
• Est. Priority Date: 10/12/2004
• Status: Expired due to Fees

• Current Assignee: Sensata Technologies Incorporated (Sensata Technologies Holding Plc)
• Original Assignee: Melexis Tessenderlo NV
• Inventors: Lee, Hae-Seung, Fife, Keith G.
• Primary Examiner(s): Villecco; John M
• Application Number:
  US11/250,114
• Time in Patent Office: 1,476 Days
• Field of Search: 348/241, 348/296, 348/294, 348/302, 348/308
• US Class Current: 348/241
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/618 for random or high-frequency noise
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A method and apparatus to perform low noise reset of a pixel circuit within an active pixel image sensor.

Claims

1. An apparatus, comprising:

a pixel circuit to detect incident light and integrate an integration value during an integration period;

a rest circuit to generate multiple reset values during a single reset period, said multiple reset values being applied to said pixel circuit during said single reset period; and

an averaging module coupled to the pixel circuit to sample the integration value and to sample said multiple reset values applied to said pixel circuit during said single reset period;

said averaging module generating a modified reset value from said multiple reset values applied to said pixel circuit during said single reset period.

2. The apparatus of claim 1, wherein said averaging module comprises a plurality of sampling circuits to sample said multiple reset values applied to said pixel circuit during said single reset period.

3. The apparatus of claim 2, wherein each of the plurality of sampling circuits comprises:

an input and an output;

an input switch coupled to the input;

a sampling capacitor coupled to the input switch and a reference voltage; and

an output switch coupled to the capacitor and the output.

4. The apparatus of claim 3, wherein the modified reset value comprises a distributed reset value of said multiple reset values applied to said pixel circuit during said single reset period.

5. The apparatus of claim 3, wherein said averaging module comprises an integration capacitance, the sampling capacitor of each of the plurality of sampling circuits comprises a sampling capacitance of approximately the integration capacitance divided by a total number of the sampling capacitors.

6. The apparatus of claim 5, further comprising a readout column and a current source coupled to the readout column, wherein the pixel circuit and said averaging module are coupled to the readout column.

7. The apparatus of claim 1, wherein said averaging module comprises a sample and hold circuit to sample and hold said multiple reset values applied to said pixel circuit during said single reset period, the sample and hold circuit having a sampling bandwidth lower than a noise bandwidth associated with a reset transistor and a sense capacitor of the pixel circuit.

8. The apparatus of claim 7, wherein said averaging module further comprises a low pass filter coupled to the sample and hold circuit, the low pass filter to cut off a reset noise signal above a bandwidth cutoff of the low pass filter.

9. The apparatus of claim 7, further comprising a readout column and a current source coupled to the readout column, wherein the pixel circuit and said averaging module are coupled to the readout column, said averaging module comprising a second sample and hold circuit to sample and hold the integration value.

10. The apparatus of claim 1, wherein the averaging module comprises an analog-to-digital converter to convert the integration value to a digital integration value and said multiple reset values applied to said pixel circuit during said single reset period to corresponding digital reset values.

11. The apparatus of claim 10, wherein said averaging module is further configured to generate the modified reset value from an average of said digital reset values.

12. The apparatus of claim 10, wherein the analog-to-digital converter comprises a tracking analog-to-digital converter to digitize a difference between a first reset value and a second reset value of said multiple reset values applied to said pixel circuit during said single reset period.

13. The apparatus of claim 12, further comprising:

a readout column coupled to the pixel circuit;

a sampling circuit coupled to the readout column to sample the integration value and said multiple reset values applied to said pixel circuit during said single reset period; and

a multiplexer coupled to the sampling circuit to receive said multiple reset values applied to said pixel circuit during said single reset period from the sampling circuit and multiplex said multiple reset values applied to said pixel circuit during said single reset period to said averaging module.

14. The apparatus of claim 1, further comprising:

a reset noise reduction circuit to reduce reset noise in one of the sampled multiple reset values applied to said pixel circuit during said single reset period;

said averaging module generating a modified reset value from said multiple reset values applied to said pixel circuit during said single reset period.

15. The apparatus of claim 14, wherein said averaging module generating a modified reset value from the sampled multiple reset values applied to said pixel circuit during said single reset period and the sampled multiple reset values applied to said pixel circuit during said single reset period having a reduced reset noise.

16. The apparatus of claim 15, wherein said averaging module averages the sampled multiple reset values applied to said pixel circuit during said single reset period to generate the modified reset value.

17. The apparatus of claim 15, further comprising means for subtracting the modified reset value from the integration value.

18. The apparatus of claim 14, further comprising means for converting the sampled multiple reset values applied to said pixel circuit during said single reset period digital reset values.

19. The apparatus of claim 14, further comprising means for erasing image lag.

20. The apparatus of claim 19, further comprising means for reducing hard reset noise introduced by a hard reset.

21. The apparatus of claim 14, further comprising means for reducing a total noise in the photo response value.

22. A method, comprising:

sampling an integration value from a pixel circuit, the integration value corresponding to a first frame;

generating multiple reset values during a single reset period, the multiple reset values being applied to the pixel circuit during the single reset period;

sampling the multiple reset values being applied to the pixel circuit during the single reset period, the multiple reset values being applied to the pixel circuit during the single reset period corresponding to a subsequent frame; and

generating a modified reset value from the sampled multiple reset values being applied to the pixel circuit during the single reset period.

23. The method of claim 22, further comprising averaging the sampled multiple reset values being applied to the pixel circuit during the single reset period to generate the modified reset value.

24. The method of claim 23, further comprising subtracting the modified reset value from the integration value.

25. The method of claim 22, further comprising holding the sampled multiple reset values being applied to the pixel circuit during the single reset period in a plurality of sampling capacitors having a total sampling capacitance approximately equal to an integration capacitance of an integration capacitor to hold the integration value.

26. The method of claim 22, further comprising sampling and holding the multiple reset values being applied to the pixel circuit during the single reset period in a reset circuit having a sampling bandwidth lower than a noise bandwidth associated with a reset transistor and a sense capacitor of the pixel circuit.

27. The method of claim 26, further comprising subtracting the modified reset value from the integration value.

28. The method of claim 22, wherein the multiple reset values being applied to the pixel circuit during the single reset period comprise only hard reset values.

29. The method of claim 22, wherein the multiple reset values being applied to the pixel circuit during the single reset period comprise only soft reset values.

30. The method of claim 22, wherein the multiple reset values being applied to the pixel circuit during the single reset period comprise one or more reset value pairs, each reset value pair comprising a hard reset value a corresponding soft reset value.

31. The method of claim 22, further comprising:

converting the sampled integration value to a digital integration value; and

converting the sampled multiple reset values being applied to the pixel circuit during the single reset period to digital reset values.

32. The method of claim 31, further comprising averaging the digital reset values to generate the modified reset value.

33. The method of claim 32, further comprising subtracting the modified reset value from the integration value.

34. The method of claim 32, wherein the digital reset values comprises a digital tracking value corresponding to a difference between two consecutive reset values of the sampled multiple reset values being applied to the pixel circuit during the single reset period.