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Logic process DRAM

  • US 7,609,538 B1
  • Filed: 06/09/2006
  • Issued: 10/27/2009
  • Est. Priority Date: 06/28/2000
  • Status: Expired due to Term
First Claim
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1. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:

  • a plurality of bit line pairs,wherein each bit line pair includes a first bit line and a second bit line, wherein the first bit line and the second bit line within each bit line pair are aligned adjacent to each other;

    a plurality of word lines,wherein each word line is associated with the bit lines such that an array is formed by the bit lines and the associated word lines;

    a first interconnect layer and a second interconnect layer,wherein each of the bit lines is associated with both the first and second interconnect layers;

    a plurality of memory cells,wherein each of the plurality of memory cells is associated with every other bit line along each word line; and

    a plurality of amplifiers,wherein each of the plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.

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