Logic process DRAM

• US 7,609,538 B1
• Filed: 06/09/2006
• Issued: 10/27/2009
• Est. Priority Date: 06/28/2000
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Sutardja, Sehat, Lee, Peter
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/449,957
• Time in Patent Office: 1,236 Days
• Field of Search: 365/63, 365/72, 365/189.02, 365/230.02, 365/51
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line and a second bit line. The first bit line and the second bit line within each bit line pair are aligned adjacent to each other. Each of a plurality of word lines is associated with the bit lines such that an array is formed by the bit lines and the associated word lines. Each bit line is associated with both first and second interconnect layers. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.

Claims

1. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:

a plurality of bit line pairs,

wherein each bit line pair includes a first bit line and a second bit line, wherein the first bit line and the second bit line within each bit line pair are aligned adjacent to each other;

a plurality of word lines,

wherein each word line is associated with the bit lines such that an array is formed by the bit lines and the associated word lines;

a first interconnect layer and a second interconnect layer,

wherein each of the bit lines is associated with both the first and second interconnect layers;

a plurality of memory cells,

wherein each of the plurality of memory cells is associated with every other bit line along each word line; and

a plurality of amplifiers,

wherein each of the plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.

2. The semiconductor integrated circuit device of claim 1, wherein, for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are associated with one of the plurality of memory cells.

3. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit further comprises:

a plurality of multiplexers in communication with a voltage source input and with a first bit line and a second bit line within a bit line pair.

4. The semiconductor integrated circuit device of claim 3, wherein the DRAM unit further comprises:

a dummy word line,

wherein the DRAM unit is configured to detect signal levels in a common mode by activating the dummy word line and detecting a signal level of an activated word line differentially as compared to a signal level of the activated dummy word line.

5. The semiconductor integrated circuit device of claim 4, wherein the first bit line and the second bit line within at least one bit line pair are twisted at least one point such that half of each bit line is associated with the first interconnect layer and half of each bit line is associated with the second interconnect layer.

6. The semiconductor integrated circuit device of claim 1, wherein the first interconnect layer comprises a first metal layer and the second interconnect layer comprises a second metal layer.

7. The semiconductor integrated circuit device of claim 1, wherein the first interconnect layer comprises a metal layer and the second interconnect layer comprises a polysilicon layer.

8. The semiconductor integrated circuit device of claim 1, wherein the first interconnect layer comprises a polysilicon layer and the second interconnect layer comprises a metal layer.

9. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit is manufactured using a logic process.

10. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit is manufactured using a DRAM process.

11. An apparatus for reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, comprising:

a plurality of pairs of bit line means for conducting electrical signals,

wherein each pair of bit line means includes a first bit line means and a second bit line means,

wherein the first bit line means and the second bit line means within each pair of bit line means are aligned adjacent to each other;

a plurality of word line means,

wherein each word line means is associated with the bit line means such that an array is formed by the bit line means and the associated word line means;

a first interconnect layer means and a second interconnect layer means, wherein each bit line means within each pair of bit line means is associated with both the first and second interconnect layer means;

a plurality of means for storing data,

wherein each of the plurality of means for storing data is associated with every other bit line means along each word line means; and

a plurality of means for amplifying,

wherein each of the plurality of means for amplifying is in communication with a first bit line means and a second bit line means within a pair of bit line means.

12. The apparatus of claim 11, wherein, for each word line means, each bit line means that is not associated with one of the plurality of means for storing data acts as a shield between bit line means that are associated with one of the plurality of means for storing data.

13. The apparatus of claim 11, further comprising:

a plurality of means for multiplexing in communication with a voltage source input means and with a first bit line means and a second bit line means within a pair of bit line means.

14. The apparatus of claim 13, wherein the apparatus further comprises:

a dummy word line means for conducting electrical signals; and

means for detecting signal levels in a common mode by activating the dummy word line means and detecting a signal level of an activated word line means differentially as compared to a signal level of the activated dummy word line means.

15. The apparatus of claim 14, wherein the first bit line means and the second bit line means within at least one pair of bit line means are twisted at least one point such that half of each bit line means is associated with the first interconnect layer means and half of each bit line means is associated with the second interconnect layer means.

16. The apparatus of claim 11, wherein the first interconnect layer means comprises a first metal layer and the second interconnect layer means comprises a second metal layer.

17. The apparatus of claim 11, wherein the first interconnect layer means comprises a metal layer and the second interconnect layer means comprises a polysilicon layer.

18. The apparatus of claim 11, wherein the first interconnect layer means comprises a polysilicon layer and the second interconnect layer means comprises a metal layer.

19. The apparatus of claim 11, wherein the DRAM device is manufactured using a logic process.

20. The apparatus of claim 11, wherein the DRAM device is manufactured using a DRAM process.

21. A method of reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, the DRAM device including a plurality of bit line pairs, a plurality of word lines, a plurality of memory cells, a first interconnect layer and a second interconnect layer, and a plurality of amplifiers, wherein each bit line pair includes a first bit line and a second bit line, the method comprising the steps of associating each of the bit lines with both the first and second interconnect layers;

aligning the first bit line and the second bit line within each bit line pair to be adjacent to each other;

associating each word line with the bit lines such that an array is formed by the bit lines and the associated word lines;

associating each of the plurality of memory cells with every other bit line along each word line; and

bringing each of the plurality of amplifiers into communication with a first bit line and a second bit line within a bit line pair.

22. The method of claim 21, wherein, for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are associated with one of the plurality of memory cells.

23. The method of claim 21, wherein the DRAM device further includes a plurality of multiplexers, the method further comprising the step of

bringing the each of the plurality of multiplexers into communication with a voltage source input and with a first bit line and a second bit line within a bit line pair.

24. The method of claim 21, wherein the DRAM device further includes a dummy word line, the method further comprising the step of

detecting signal levels in a common mode by activating the dummy word line and detecting a signal level of an activated word line differentially as compared to a signal level of the activated dummy word line.

25. The method of claim 24, further comprising the step of:

twisting the first bit line and the second bit line within at least one pair of bit lines at least one point such that half of each bit line is associated with the first interconnect layer and half of each bit line is associated with the second interconnect layer.

26. The method of claim 21, wherein the first interconnect layer comprises a first metal layer and the second interconnect layer comprises a second metal layer.

27. The method of claim 21, wherein the first interconnect layer comprises a metal layer and the second interconnect layer comprises a polysilicon layer.

28. The method of claim 21, wherein the first interconnect layer comprises a polysilicon layer and the second interconnect layer comprises a metal layer.

29. The method of claim 21, wherein the DRAM device is manufactured using a logic process.

30. The method of claim 21, wherein the DRAM device is manufactured using a DRAM process.