Semiconductor device

• US 7,609,545 B2
• Filed: 07/26/2008
• Issued: 10/27/2009
• Est. Priority Date: 01/05/2005
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Osada, Kenichi, Kawahara, Takayuki
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US12/180,523
• Publication Number:
  US 20080285336A1
• Time in Patent Office: 458 Days
• Field of Search: 365/163, 365/148, 365/113
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

Claims

1. A semiconductor device that accesses a memory cell based on a row address and a column address comprising:

a memory array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines, and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;

a plurality of word drivers connected to each of said plurality of word lines;

a column selection circuit connected to said plurality of bit lines and that selects some of said plurality of bit lines to connect to a plurality of read circuits and a plurality of write circuits;

an address hold circuit storing a row address and a column address involved with the previous access cycle; and

an address compare circuit,

wherein said word line is selected by decoding said row address, and said column selection circuit is selected by decoding said column address;

wherein said address compare circuit is a circuit that compares a row address and a column address involved with a current access cycle and said row address and said column address held in said address hold circuit;

wherein each of said memory cells comprises a selection element and a storage element connected in series to corresponding one line of said plurality of bit lines, a control electrode of said selection element is connected to corresponding one line of said plurality of word lines,

wherein said storage element is an element to store data according to variations in resistance;

wherein said word line is not turned on when said address compare circuit detects, in successive read cycles, that both of the row address and column address involved with a current access cycle match the row address and column address involved with the previous access cycle respectively.

2. A semiconductor device according to claim 1, further comprising;

a precharge circuit,

wherein said precharge circuit precharges said bit line to be selected by said column selection circuit, and does not precharge the other bit lines within said memory array.

3. A semiconductor device according to claim 1,

wherein, in successive read access cycles, when said address compare circuit detects that both of the row address and column address involved with a current access cycle match the row address and column address involved with the previous access cycle respectively, said semiconductor device outputs the value of said read circuit.

4. A semiconductor device according to claim 1,

wherein said storage element is a phase change element.

5. A semiconductor device comprising:

a memory array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines, and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;

a plurality of word drivers connected to each of said plurality of word lines;

a plurality of read circuits connected to said plurality of bit lines; and

a circuit for correcting errors,

wherein each of said plurality of memory cells has a selection element and a storage element connected in series to corresponding one line of said plurality of bit lines, and the control electrode of said selection element is connected to corresponding one line of said plurality of word lines;

wherein said storage element is an element that stores data according to the variations in resistance; and

wherein when an error bit is detected by said error checking and correction, the data that has been corrected by said error checking and correction is written.

6. A semiconductor device according to claim 5,

wherein said storage element is a phase change element.

7. A semiconductor device according to claim 6,

wherein, when an error bit is detected by said error checking and correction, only the amorphousizing of said phase change element is performed.

8. A semiconductor device according to claim 5,

wherein a read for said error correction is performed with a narrower margin than for a normal read.

9. A semiconductor device according to claim 5,

wherein said reset operation is hidden in a normal access cycle.