Semiconductor memory device

• US 7,609,551 B2
• Filed: 09/25/2007
• Issued: 10/27/2009
• Est. Priority Date: 09/29/2006
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohsawa, Takashi, Fukuda, Ryo, Shino, Tomoaki, Aochi, Hideaki, Hamamoto, Takeshi, Nitayama, Akihiro
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US11/860,956
• Publication Number:
  US 20080237695A1
• Time in Patent Office: 763 Days
• Field of Search: 365/185.08
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

Claims

1. A semiconductor memory device comprising:

a semiconductor layer;

a charge trapping film provided on a first surface of the semiconductor layer;

a gate insulating film provided on a second surface opposing the first surface of the semiconductor layer;

a back gate provided on the charge trapping film;

a front gate provided on the gate insulating film;

a source and a drain formed in the semiconductor layer; and

a body region which is provided between the drain and the source, the body region being in an electrically floating state, wherein

the semiconductor memory device includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and

the semiconductor memory device is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

2. The semiconductor memory device according to claim 1 further comprising:

a bit line connected to the drain; and

a source line connected to the source, wherein

voltages are applied between the front gate and the back gate, the drain and the back gate, and the source and the back gate, so that the number of majority carriers in the body region of a memory cell is converted into the amount of charges in the charge trapping film, the memory cell including the source, the drain, the body region, the charge trapping film, the gate insulating film, the back gate, and the front gate.

3. The semiconductor memory device according to claim 1, wherein a plurality of memory cells are arranged in a matrix, each memory cell including the source, the drain, the body region, the charge trapping film, the gate insulating film, the back gate, and the front gate,

the semiconductor memory device further comprising:

a plurality of bit lines connected to the drains of the memory cells arranged in a column direction; and

a source line connected to the sources, wherein

a plurality of the front gates are arranged in a column direction,

voltages are applied to a first front gate of the plurality of front gates and to a first bit line of the plurality of bit lines, so that charges are injected in the charge trapping film of a first memory cell connected to the first front gate and the first bit line.

4. The semiconductor memory device according to claim 1, further comprising:

a plurality of memory cells arranged in a matrix, each memory cell including the source, the drain, the body region, the charge trapping film, the gate insulating film, the back gate, and the front gate,

a plurality of bit lines connected to the drains arranged in a column direction; and

a plurality of source lines connected to the sources arranged in a row direction,

wherein

voltages are applied to a first bit line of the plurality of bit lines and to a first source line of the plurality of source lines, so that charges are injected in the charge trapping film of a first memory cell connected to the first bit line and the first source line.

5. The semiconductor memory device according to claim 3 further comprising sense amplifiers provided for the bit lines, wherein

a first sense amplifier of the sense amplifiers connected to the first bit line identifies data of memory cells in the first storage state for each of the front gates and shifts the memory cells to the second storage state selectively based on the data,

or the first sense amplifier connected to the first bit line identifies data of the memory cells in the second storage state for each of the front gates and shifts the memory cells to the first storage state selectively based on the data.

6. The semiconductor memory device according to claim 1 further comprising:

a plurality of memory cells arranged in a matrix, each memory cell including the source, the drain, the body region, the charge trapping film, the gate insulating film, the back gate, and the front gate;

a plurality of bit lines connected to the drains arranged in a column direction;

a source line connected to the sources; and

sense amplifiers provided for the bit lines, wherein

a first sense amplifier of the sense amplifiers performs a charge injection operating injecting charges in the charge trapping film of a first memory cell of the memory cells, then the first sense amplifier performs a restore operation reading data based on the first storage state of a second memory cell, and writing the data back in the second memory cell.

7. The semiconductor memory device according to claim 6, wherein

after injecting charges in the charge trapping film of the first memory cell, charges are injected again in the charge trapping film of the first memory cell, when a current flowing in the first memory cell at the time of data reading is smaller than a predetermined target value.

8. The semiconductor memory device according to claim 6, wherein

the charge injection operation to the first memory cell is divided into a plurality of sub-injection operations, the restore operation to the second memory cell being performed between the sub-injection operations.

9. The semiconductor memory device of claim 1, wherein

a plurality of memory cells are arranged in a matrix, each memory cell including the source, the drain, the body region, the charge trapping film, the gate insulating film, the back gate, and the front gate,

the semiconductor memory device further comprising:

a plurality of bit lines connected to the drains of the memory cells arranged in a column direction; and

a source line connected to the sources,

wherein

a plurality of the front gates are arranged in a column direction,

a plurality of back gates are provided so as to correspond to the front gates,

voltages are applied to a first front gate of the plurality of front gates and to a first back gate of the plurality of back gates and to a first bit line of the plurality of bit lines to inject charges in the charge trapping films of a memory cell connected to the first front gate, the first back gate and the first bit line.

10. The semiconductor memory device according to claim 9 further comprising sense amplifiers provided for the bit lines, wherein

a first sense amplifier of the sense amplifiers connected to the first bit line identifies data of memory cells in the first storage state for each of the front gates and shifts the memory cells to the second storage state selectively based on the data,

or the first sense amplifier connected to the first bit line identifies data of memory cells in the second storage state for each of the front gates and shifts the memory cells to the first storage state selectively based on the data.

11. The semiconductor memory device according to claim 9 further comprising sense amplifiers provided for the bit lines, wherein

a first sense amplifier of the sense amplifiers connected to the first bit line injects charges in the charge trapping film of a first memory cell of the memory cells connected to the first front gate, then read data based on the first storage state of a second memory cell of the memory cells which is connected to a second front gate different from the first front gate, and the first sense amplifier restores the data back in the second memory cell.

12. The semiconductor memory device of claim 1, wherein, when data of a memory cell in the first storage state is read, the back gate is biased to a polarity opposite to that of the majority carriers with respect to the source potential.

13. The semiconductor memory device according to claim 1, wherein, when data of a memory cell in the second storage state is read, a voltage is applied to the back gate so that the first surface of the body region is depleted.

14. The semiconductor memory device according to claim 1 wherein charges in the charge trapping film are placed near the junction between the source and the body region or near the junction between the drain and the body region in the second storage state.

15. A semiconductor memory device comprising:

a semiconductor layer;

a charge trapping film provided on a first surface of the semiconductor layer;

a gate insulating film provided on a second surface opposing the first surface of the semiconductor layer;

a back gate provided on the charge trapping film;

a front gate provided on the gate insulating film;

a source and a drain formed in the semiconductor layer; and

a body region which is provided between the drain and the source, the body region being in an electrically floating state, wherein

the semiconductor memory device includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and

the data is stored in both states of the first storage state and the second storage state.

16. The semiconductor memory device of claim 15, further comprising:

a plurality of memory cells arranged in a matrix, each memory cell including the source, the drain, the body region, the charge trapping film, the gate insulating film, the back gate, and the front gate,

a plurality of bit lines connected to the drains of the memory cells arranged in a column direction; and

a source line connected to the sources,

wherein

a plurality of the front gates are arranged in a column direction,

a plurality of back gates are provided so as to correspond to the front gates,

voltages are applied to a first front gate of the plurality of front gates and to a first back gate of the plurality of back gates and to a first bit line of the plurality of bit lines to inject charges in the charge trapping films of a memory cell connected to the first front gate, the first back gate and the first bit line.

17. The semiconductor memory device according to claim 15, wherein,

the semiconductor memory device converts the number of majority carriers in the body region into the amount of charges in the charge trapping film or converts the amount of charges in the charge trapping film into the number of majority carriers in the body region.

18. The semiconductor memory device of claim 15, wherein, when data of a memory cell in the first storage state is read, the back gate is biased to a polarity opposite to that of the majority carriers with respect to the source potential.

19. The semiconductor memory device according to claim 15, wherein, when data of a memory cell in the second storage state is read, a voltage is applied to the back gate so that the first surface of the body region is depleted.

20. The semiconductor memory device according to claim 15 wherein charges in the charge trapping film are placed near the junction between the source and the body region or near the junction between the drain and the body region in the second storage state.