Non-volatile memory with background data latch caching during erase operations
First Claim
1. A non-volatile memory device having addressable pages of memory cells, comprising:
- a sense amplifier and a set of data latches for each memory cell of an addressed page, said set of data latches dedicated to the sense amplifier for latching data read from the memory cell and for referencing data to be programmed to the memory cell;
a state machine for controlling an erase memory operation on a designated group of pages; and
for performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array, wherein said operations are performed contemporaneously with the erase operation.
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Accused Products
Abstract
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.
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Citations
20 Claims
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1. A non-volatile memory device having addressable pages of memory cells, comprising:
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a sense amplifier and a set of data latches for each memory cell of an addressed page, said set of data latches dedicated to the sense amplifier for latching data read from the memory cell and for referencing data to be programmed to the memory cell; a state machine for controlling an erase memory operation on a designated group of pages; and for performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array, wherein said operations are performed contemporaneously with the erase operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20)
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18. A non-volatile memory device having addressable pages of memory cells, comprising:
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a sense amplifier and a set of data latches for each memory cell of an addressed page, said set of data latches dedicated to the sense amplifier for latching data read from the memory cell and for referencing data to be programmed to the memory cell; means for controlling an erase memory operation on a designated group of pages; and means for performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array, wherein said operations are performed contemporaneously with the erase operation.
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Specification