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Non-volatile memory with background data latch caching during erase operations

  • US 7,609,552 B2
  • Filed: 05/05/2006
  • Issued: 10/27/2009
  • Est. Priority Date: 04/01/2005
  • Status: Active Grant
First Claim
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1. A non-volatile memory device having addressable pages of memory cells, comprising:

  • a sense amplifier and a set of data latches for each memory cell of an addressed page, said set of data latches dedicated to the sense amplifier for latching data read from the memory cell and for referencing data to be programmed to the memory cell;

    a state machine for controlling an erase memory operation on a designated group of pages; and

    for performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array, wherein said operations are performed contemporaneously with the erase operation.

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