Signaling for entry point frames with predicted first field

• US 7,609,762 B2
• Filed: 11/15/2004
• Issued: 10/27/2009
• Est. Priority Date: 09/07/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Crinon, Regis J., Srinivasan, Sridhar, Regunathan, Shankar, Holcomb, Thomas W.
• Primary Examiner(s): Dastouri; Mehrdad
• Assistant Examiner(s): Werner; David N.
• Application Number:
  US10/989,843
• Publication Number:
  US 20050152448A1
• Time in Patent Office: 1,807 Days
• Field of Search: 375/240.13
• US Class Current: 375/240.13
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 21/23424 involving splicing one content stream with another content stream, e.g. for inserting or substituting an advertisement
• CPC Class Codes: H04N 21/44016 involving splicing one content stream with another content stream, e.g. for substituting a video clip
• CPC Class Codes: H04N 21/8455 involving pointers to the content, e.g. pointers to the I-frames of the video stream

Abstract

A video decoder receives an entry point key frame comprising first and second interlaced video fields and decodes a first syntax element comprising information (e.g., frame coding mode) for the entry point key frame at a first syntax level (e.g., frame level) in a bitstream. The first interlaced video field is a predicted field, and the second interlaced video field is an intra-coded field. The information for the entry point key frame can be a frame coding mode (e.g., field interlace) for the entry point key frame. The decoder can decode a second syntax element at the first syntax level comprising second information (e.g., field type for each of the first and second interlaced video fields) for the entry point key frame.

Claims

1. In a computing device that implements a video encoder, a method comprising:

with the computing device that implements the video encoder, for an entry point key frame comprising first and second interlaced video fields, inserting a first syntax element for the entry point key frame at a first syntax level in a bitstream, wherein the first syntax element is a frame coding mode for the entry point key frame, and wherein the frame coding mode indicates that the first and second interlaced video fields are arranged in the bitstream for decoding as individual fields; and

with the computing device that implements the video encoder, inserting a second syntax element at the first syntax level in the bitstream, wherein the second syntax element indicates a field type for each of the first and second interlaced video fields in the entry point key frame, the second syntax element indicating a combination of different field types for the first and second interlaced video fields, respectively, in the entry point key frame, wherein the combination of different field types is P/I for the first and second interlaced video fields, respectively, wherein the first interlaced video field in the entry point key frame is a P-field, and wherein the second interlaced video field in the entry point key frame is an intra-coded field.

2. The method of claim 1 wherein the frame coding mode is field interlace.

3. The method of claim 1 wherein the first syntax element is a variable length code.

4. The method of claim 1 wherein the second syntax element is a fixed length code.

5. The method of claim 1 further comprising inserting an entry point start code and entry point header before the first syntax element.

6. The method of claim 1 wherein the first syntax level in the bitstream is frame level.

7. In a computing device that implements a video decoder, a method comprising:

receiving, at the computing device that implements the video decoder, an entry point key frame comprising first and second interlaced video fields;

with the computing device that implements the video decoder, decoding a first syntax element for the entry point key frame at a first syntax level in a bitstream, wherein the first syntax element is a frame coding mode for the entry point key frame, and wherein the frame coding mode indicates that the first and second interlaced video fields are arranged in the bitstream for decoding as individual fields; and

with the computing device that implements the video decoder, decoding a second syntax element for the entry point key frame at the first syntax level in the bitstream, wherein the second syntax element indicates a field type for each of the first and second interlaced video fields in the entry point key frame, wherein the second syntax element can indicate one of plural different combinations of field types for the first and second interlaced video fields, respectively, the plural different combinations of field types including P/I, wherein the first interlaced video field in the entry point key frame is a P-field, and wherein the second interlaced video field in the entry point key frame is an intra-coded field.

8. The method of claim 7 wherein the frame coding mode is field interlace.

9. The method of claim 7 wherein the second syntax element is a single code that jointly indicates the field type of the first interlaced video field and the field type of the second interlaced video field of the entry point key frame.

10. The method of claim 9 wherein the second syntax element is a fixed length code.

11. The method of claim 7 further comprising:

receiving, at the computing device that implements the video decoder, an entry paint header and entry point start code associated with the entry point key frame; and

with the computing device that implements the video decoder, decoding the entry point header and the entry point start code.

12. The method of claim 7 wherein the first syntax level in the bitstream is frame level.

13. The method of claim 7 further comprising:

receiving, at the computing device that implements the video decoder, the entry point key frame in an elementary stream buffer;

with the computing device that implements the video decoder, decoding a start code for the second interlaced video field after determining the field type for the second interlaced video field; and

with the computing device that implements the video decoder, decoding the second interlaced video field;

wherein decoding of the first interlaced video field is omitted after determining the field type for the first interlaced video field.

15. The method of claim 7 wherein the first syntax element is a variable length code, and wherein the second syntax element is a single fixed length code that jointly indicates the field type of the first interlaced video field and the field type of the second interlaced video field of the entry point key frame.

14. In a computing device that implements a video decoder, a method comprising:

receiving, at the computing device that implements the video decoder, an entry point key frame comprising first and second interlaced video fields;

with the computing device that implements the video decoder, decoding a first syntax element for the entry point key frame at frame level in a bitstream, the first syntax element comprising a variable length code for a frame coding mode for the entry point key frame, wherein the frame coding mode indicates that the first and second interlaced video fields are arranged in the bitstream for decoding as individual fields; and

with the computing device that implements the video decoder, decoding a second syntax element for the entry point key frame at frame level in the bitstream, the second syntax element comprising a single fixed length code that jointly indicates a field type for each of the first and second interlaced video fields, the second syntax element indicating a combination of different field types for the first and second interlaced video fields, respectively, in the entry point key frame, wherein the combination of different field types is P/I for the first and second interlaced video fields, respectively, wherein the first interlaced video field in the entry point key frame is a P-field, and wherein the second interlaced video field in the entry point key frame is an intra-coded field.