System and method for memory hub-based expansion bus

• US 7,610,430 B2
• Filed: 03/10/2008
• Issued: 10/27/2009
• Est. Priority Date: 03/25/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Knoll; Clifford H
• Application Number:
  US12/075,424
• Publication Number:
  US 20080222379A1
• Time in Patent Office: 596 Days
• Field of Search: 710/311, 710/312, 710/316, 711/119, 711/5, 365/230.01, 365/230.03, 370/423, 370/912
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: Y10S 370/912 Packet communications

Abstract

A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Claims

1. A memory system, comprising:

a memory hub controller;

a memory bus coupled to the memory hub controller;

a plurality of memory modules each having a memory hub coupled to the memory bus, each of the memory modules further having a plurality of memory devices coupled to the respective memory hub and the memory hub configured to issue memory requests to only the memory devices coupled thereto in response to memory requests from the memory hub controller; and

at least one expansion module each having a processor unit coupled to the memory bus, each of the at least one expansion module further having a plurality of memory devices coupled to the respective processor unit, each processor unit configured to provide memory requests to the memory devices of the respective expansion module and at least one of the memory devices of one of the memory modules and receive memory responses from the memory devices to which the memory requests are provided.

2. The memory system of claim 1 wherein the processor unit of one of the at least one expansion module is a graphics controller.

3. The memory system of claim 1 wherein the processor unit of each of the at least one expansion module is for a respective purpose different than the respective purpose of the processor unit of another of the at least one expansion module.

4. The memory system of claim 3 wherein the processor unit of one of the at least one expansion module is a graphics controller, and wherein the processor unit of another of the at least one expansion module is an input/output processor.

5. The memory system of claim 1 wherein memory requests from each of the at least one expansion module are primarily serviced by a respective one of the memory modules and the memory devices of the respective expansion module.

6. An electronic device, comprising:

a processor;

a memory hub controller coupled to the processor;

a plurality of memory modules each having a memory hub coupled to the memory hub controller, each of the memory modules having a plurality of memory devices coupled to the respective memory hub and configured to issue local memory requests in response to memory requests issued by the memory hub controller to only the memory devices coupled to the memory hub and provide memory responses to the memory hub controller;

an expansion module having a processor unit coupled to at least one of the memory modules, the expansion module further having a plurality of memory devices coupled to the processor unit and configured to provide memory responses to the processor unit responsive to receiving memory requests from the processor unit, the processor unit configured to provide memory requests to and receive memory responses from at least one of the memory devices of the at least one of the memory modules.

7. The electronic device of claim 6, further comprising first and second devices, the first device coupled to receive data from the memory hub controller but not the expansion module, the second device coupled to receive data from the expansion module but not the memory hub controller.

8. The electronic device of claim 6 wherein the expansion module comprises a plurality of expansion modules each having a processor unit and a plurality of memory devices coupled to the respective processor unit, each expansion module coupled to at least a respective one of the memory modules, memory requests from each processor unit being serviced by the respective memory devices of the respective expansion module and at least one memory device of the respective one of the memory modules.

9. The electronic device of claim 6 wherein at least one memory device of the at least one of the memory modules coupled to the expansion module primarily services memory requests from the expansion module while memory devices of at least one other memory module primarily service memory requests from the memory hub controller.

10. The electronic device of claim 6 wherein the memory hub controller and the expansion module each accesses the memory modules independently.

11. A method of accessing data stored in a plurality of memory devices in a plurality of memory modules coupled to each other and to a memory controller, comprising:

issuing a memory request from the memory controller to at least one of the memory modules;

receiving the memory request from the memory controller by a memory hub for the at least one of the memory modules and issuing a local memory request to memory devices coupled thereto, the memory hub limited to issuing local memory requests to the coupled memory devices;

issuing a memory request from a first expansion module coupled to a first of the memory modules to the first of the memory modules;

providing a memory response from the at least one of the memory modules to the memory controller responsive to the memory request from the memory controller; and

providing a memory response from the first of the memory modules to the first expansion module responsive to the memory request from the first expansion module.

12. The method of claim 11 wherein the at least one of the memory modules providing the memory response to the memory controller is not the first of the memory modules.

13. The method of claim 11 wherein the at least one of the memory modules providing the memory response to the memory controller includes the first of the memory modules.

14. The method of claim 11, further comprising:

issuing a memory request from a second expansion module coupled to a second of the memory modules to the second of the memory modules; and

providing a memory response from the second of the memory modules to the second expansion module responsive to the memory request from the second expansion module.

15. The method of claim 14 wherein at least one of the memory devices in the first of the memory modules primarily services memory requests from the first expansion module, and wherein at least one of the memory devices in the second of the memory modules primarily services memory requests from the second expansion module.

16. A method of receiving memory requests and providing memory responses to and from memory devices in a module in a memory system, comprising:

receiving a memory request on a system bus;

in response to receiving the memory request, issuing a local memory request from a memory hub coupled to memory devices of a module, the memory hub limited to issuing local memory requests to the memory devices of the module;

locally accessing data on a local bus responsive to the local memory request and providing a first memory response;

locally generating and processing a memory request independently of receiving the memory request on the system bus;

locally accessing data on the local bus responsive to the locally generated memory request and providing a second memory response; and

coupling the first and second memory responses from the local bus to the system bus.

17. The method of claim 16 wherein locally generating and processing a memory request comprises generating and processing a memory request for graphics data.

18. The method of claim 16 wherein locally generating and processing a memory request comprises generating command packets that include identification data for identify the memory module.

19. The method of claim 16 further comprising coupling input and output devices to the memory module through a high-speed input/output bus.

20. The method of claim 16 wherein the system bus comprises a downstream bus and an upstream bus.

21. A method of providing memory requests to a plurality of memory modules of a memory system, comprising:

coupling a subprocessor independently from a memory system controller of the memory system to a memory hub of at least one of the memory modules, the memory hub having a plurality of memory devices and configured to issue local memory requests to only the plurality of memory devices;

providing memory requests generated by the subprocessor to the memory hub of the at least one of the memory modules; and

receiving memory responses from the plurality of memory devices and from the memory hub of the at least one of the memory modules independent of the memory system controller.

22. The method of claim 21, further comprising receiving memory requests from the system controller and providing memory responses from the plurality of memory devices responsive to receiving the memory requests from the memory system controller.

23. The method of claim 21 wherein the memory requests comprise command packets that include information identifying the subprocessor or the memory hub of the at least one of the modules to which the command packets are directed towards.

24. The method of claim 21 wherein the subprocessor is directly coupled to input and output devices through a high-speed input/output bus.

25. The method of claim 21 wherein receiving memory responses from the plurality of memory devices and the memory hub of the at least one of the memory modules comprises receiving graphics data.