Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

• US 7,611,980 B2
• Filed: 08/30/2006
• Issued: 11/03/2009
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wells, David H., Abatchev, Mirzafer K.
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Chang; Leonard
• Application Number:
  US11/514,117
• Publication Number:
  US 20080057692A1
• Time in Patent Office: 1,161 Days
• Field of Search: 438/424, 438/947, 438/702, 438/942, 257/435, 257/797, 257/798, 257/E21.023, 257/E21.035, 257/E21.038, 257/E21.24
• US Class Current: 438/597
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/946 Step and repeat
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Claims

1. A method for fabricating an integrated circuit, comprising:

providing a first mandrel over a substrate, the first mandrel having a first width;

providing a second mandrel substantially over the first mandrel, the second mandrel having a second width smaller than the first width;

providing a layer of spacer material on the first and second mandrels;

subjecting the layer of spacer material to a spacer etch, wherein the spacer etch simultaneously forms spacers on sidewalls of the first and second mandrels;

selectively removing at least portions of the mandrels relative to the spacers to form a spacer pattern defined by the spacers; and

processing the substrate through a mask defined by the spacer pattern.

2. The method of claim 1, wherein processing comprises etching to transfer the spacer pattern to the substrate.

3. The method of claim 2, further comprising transferring the spacer pattern to a lower hard mask layer and removing the spacers prior to processing.

4. The method of claim 3, wherein the substrate comprises an upper interlevel dielectric layer and processing through the mask forms damascene trenches.

5. The method of claim 4, wherein the spacer pattern comprises elongated lines with connecting loop ends, and the method further comprises blocking the loop ends prior to processing.

6. The method of claim 3, wherein providing the first mandrel over the substrate comprises providing the first mandrel over a conductor.

7. The method of claim 6, wherein the spacer pattern comprises elongated lines with connecting loop ends, and the method further comprises removing the loop ends prior to processing.

8. The method of claim 1, wherein providing the second mandrel comprises providing the second mandrel extending parallel to the first mandrel.

9. The method of claim 1, wherein providing the second mandrel comprises providing the second mandrel centered with respect to the first mandrel.

10. The method of claim 1, wherein simultaneously forming the spacers provides the spacers with a third width that is smaller than the first width.

11. The method of claim 1, wherein providing the second mandrel comprises using photolithography with a resolution limit greater than about 200 nm.

12. The method of claim 1, further comprising providing a third mandrel on the second mandrel, the third mandrel having a third width.

13. The method of claim 12, wherein providing the third mandrel comprises providing the third mandrel having the third width smaller than the second width.

14. The method of claim 13, wherein providing the third mandrel comprises providing the third mandrel centered with respect to the second mandrel.

15. The method of claim 1, wherein selectively removing comprises removing portions of the first mandrel.

16. The method of claim 1, wherein selectively removing comprises leaving portions of the first mandrel directly below spacers on the sidewalls of the second mandrel.

17. The method of claim 1, wherein providing the layer of spacer material comprises blanket depositing spacer material on surfaces of the substrate.

18. The method of claim 1, wherein simultaneously forming spacers comprises providing spacers having a width less than or equal to about one half times the first width minus one half times the second width.