MOS devices with source/drain regions having stressed regions and non-stressed regions

• US 7,612,364 B2
• Filed: 11/20/2006
• Issued: 11/03/2009
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Sun, Yuan-Chen, Thei, Kong-Beng, Chuang, Harry
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US11/602,100
• Publication Number:
  US 20080054250A1
• Time in Patent Office: 1,079 Days
• Field of Search: 257/19, 257/18, 257/63, 257/65, 257/190, 257/192, 257/E29.104, 257/E29.193, 257/E31.035, 257/E33.009
• US Class Current: 257/19
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a gate stack on the semiconductor substrate;

a source region comprising;

a first stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack;

a first portion of the semiconductor substrate adjoining the first stressor and on an opposite side of the first stressor from the gate stack; and

a drain region comprising;

a second stressor having at least a portion in the semiconductor substrate and on an opposite side of the gate stack than the first stressor; and

a second portion of the semiconductor substrate adjoining the second stressor and on an opposite side of the second stressor from the gate stack, wherein the first and the second stressors and the first and the second portions of the semiconductor substrate are doped with impurities of a same conductivity type.

2. The semiconductor structure of claim 1 further comprising a first insulation region in the semiconductor substrate and adjoining the first portion of the semiconductor substrate.

3. The semiconductor structure of claim 2 further comprising a second insulation region in the semiconductor substrate and adjoining the second portion of the semiconductor substrate.

4. The semiconductor structure of claim 1, wherein the conductivity type is p-type, and wherein the first stressor comprises SiGe.

5. The semiconductor structure of claim 1, wherein the conductivity type is n-type, and wherein the first stressor comprises SiC.

6. The semiconductor structure of claim 1 further comprising a silicide film on the first stressor and the first portion of the semiconductor substrate.

7. A semiconductor structure comprising:

a semiconductor substrate;

a first metal-oxide-semiconductor (MOS) device comprising;

a first gate stack on the semiconductor substrate;

a first stressor having at least a portion in the semiconductor substrate and adjacent to the first gate stack, wherein the first stressor comprises an impurity of a first conductivity type; and

a first portion of the semiconductor substrate adjoining the first stressor and on an opposite side of the first stressor from the first gate stack, wherein the first portion of the semiconductor substrate is doped with an impurity of the first conductivity type; and

a second MOS device comprising;

a second gate stack on the semiconductor substrate;

a second stressor having at least a portion in the semiconductor substrate and adjacent to the second gate stack, wherein the second stressor comprises an impurity of the first conductivity type; and

a second portion of the semiconductor substrate adjoining the second stressor and on an opposite side of the second stressor from the second gate stack, wherein the second portion of the semiconductor substrate is doped with an impurity of the first conductivity type; and

a third portion of the semiconductor substrate between and adjoining the first and the second portions of the semiconductor substrate.

8. The semiconductor structure of claim 7, wherein the third portion of the semiconductor substrate comprises an impurity of the first conductivity type.

9. The semiconductor structure of claim 7, wherein the third portion of the semiconductor substrate comprises an impurity of a second conductivity type opposite the first conductivity type.

10. The semiconductor structure of claim 7 further comprising a silicide film on the first stressor and the first portion of the semiconductor substrate.

11. The semiconductor structure of claim 7, wherein the first conductivity type is p-type, and wherein the first and the second stressors comprise SiGe.

12. The semiconductor structure of claim 7, wherein the first conductivity type is n-type, and wherein the first and the second stressors comprise SiC.

13. The semiconductor structure of claim 7, wherein the first MOS device further comprises:

a third stressor having at least a portion in the semiconductor substrate and on an opposite side of the first gate stack from the first stressor, wherein the third stressor comprises an impurity of the first conductivity type; and

an insulation region in the semiconductor substrate and spaced apart from the third stressor by a fourth portion of the semiconductor substrate, wherein the fourth portion of the semiconductor substrate is doped with an impurity of the first conductivity type.

14. The semiconductor structure of claim 7, wherein a first width of the first stressor and a third width of the third portion of the semiconductor substrate have a first ratio, and wherein a second width of the second stressor and the third width have a second ratio, and wherein each of the first and the second ratios is less than about 0.5.