Semiconductor device including a strained superlattice layer above a stress layer

• US 7,612,366 B2
• Filed: 07/13/2006
• Issued: 11/03/2009
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Mears, Robert J., Kreps, Scott A.
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US11/457,256
• Publication Number:
  US 20070007508A1
• Time in Patent Office: 1,209 Days
• Field of Search: 257 18- 20, 257/24, 257/27, 257/E29.056, 257/E29.072
• US Class Current: 257/20
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A semiconductor device comprising:

a stress layer;

a strained superlattice layer above said stress layer and comprising a plurality of stacked groups of layers;

each group of layers of said strained superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and a single non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions from among the plurality of base semiconductor portions, wherein not all of the possible sites for non-semiconductor atoms in the single non-semiconductor monolayer are occupied by non-semiconductor atoms; and

non-superlattice regions for causing transport of charge carriers through said strained superlattice layer in a parallel direction relative to the stacked groups of layers, said non-superlattice regions comprising source and drain regions with said strained superlattice layer therebetween.

2. The semiconductor device of claim 1 wherein said stress layer comprises a graded semiconductor layer.

3. The semiconductor device of claim 2 wherein said graded semiconductor layer is graded in a vertical direction;

and wherein said strained superlattice is vertically stacked on said graded semiconductor layer.

4. The semiconductor device of claim 2 further comprising a substantially ungraded semiconductor layer positioned between said graded semiconductor layer and said strained superlattice layer.

5. The semiconductor device of claim 2 wherein said graded semiconductor layer comprises graded silicon germanium.

6. The semiconductor device of claim 1 wherein said stress layer comprises a plurality of strain inducing pillars.

7. The semiconductor device of claim 1 further comprising an insulating layer positioned between said stress layer and said strained superlattice layer.

8. The semiconductor device of claim 1 further comprising a semiconductor substrate adjacent said stress layer on a side thereof opposite said strained superlattice layer.

9. The semiconductor device of claim 1 wherein said strained superlattice layer has a compressive strain.

10. The semiconductor device of claim 1 wherein said strained superlattice layer has a tensile strain.

11. The semiconductor device of claim 1 wherein said strained superlattice layer has a common energy band structure therein.

12. The semiconductor device of claim 1 wherein each of said base semiconductor portions comprises silicon.

13. The semiconductor device of claim 1 wherein each of said base semiconductor portions comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

14. The semiconductor device of claim 1 wherein each of said non-semiconductor monolayers comprises oxygen.

15. The semiconductor device of claim 1 wherein each of said non-semiconductor monolayers comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

16. The semiconductor device of claim 1 wherein each of said base semiconductor portions is less than eight monolayers thick.

17. The semiconductor device of claim 1 wherein said strained superlattice layer further has a substantially direct energy bandgap.

18. The semiconductor device of claim 1 wherein said strained superlattice layer further comprises a base semiconductor cap layer on an uppermost group of layers.

19. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

20. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

21. A semiconductor device comprising:

a stress layer comprising a semiconductor graded in a vertical direction;

a strained superlattice layer comprising a plurality of groups of layers vertically stacked on said graded semiconductor layer;

each group of layers of said strained superlattice layer comprising a plurality of stacked base silicon monolayers defining a base silicon portion and a single oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions from among the plurality of base silicon portions, wherein not all of the possible sites for oxygen atoms in the single oxygen monolayer are occupied by oxygen atoms; and

non-superlattice regions for causing transport of charge carriers through said strained superlattice layer in a parallel direction relative to the stacked groups of layers, said non-superlattice regions comprising source and drain regions with said strained superlattice layer therebetween.

22. The semiconductor device of claim 21 further comprising a substantially ungraded semiconductor layer positioned between said stress layer and said strained superlattice layer.

23. The semiconductor device of claim 21 wherein said stress layer comprises graded silicon germanium.

24. The semiconductor device of claim 21 wherein said stress layer comprises a plurality of strain inducing pillars.

25. The semiconductor device of claim 21 further comprising an insulating layer positioned between said stress layers and said strained superlattice layer.

26. The semiconductor device of claim 21 further comprising a semiconductor substrate adjacent said stress layer on a side thereof opposite said strained superlattice layer.

27. A semiconductor device comprising:

a stress layer;

a strained layer above said stress layer and comprising a plurality of stacked base semiconductor portions and a single non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions from among the plurality of base semiconductor portions, wherein not all of the possible sites for non-semiconductor atoms in the single non-semiconductor monolayer are occupied by non-semiconductor atoms; and

non-superlattice regions for causing transport of charge carriers through said strained layer in a parallel direction relative to the stacked base semiconductor portions, said non-superlattice regions comprising source and drain regions with said strained layer therebetween.

28. The semiconductor device of claim 27 wherein said stress layer comprises a graded semiconductor layer.

29. The semiconductor device of claim 28 wherein said graded semiconductor layer is graded in a vertical direction;

and wherein said strained layer is vertically stacked on said graded semiconductor layer.

30. The semiconductor device of claim 28 further comprising a substantially ungraded semiconductor layer positioned between said graded semiconductor layer and said strained layer.

31. The semiconductor device of claim 28 wherein said graded semiconductor layer comprises graded silicon germanium.

32. The semiconductor device of claim 27 wherein said stress layer comprises a plurality of strain inducing pillars.

33. The semiconductor device of claim 27 further comprising an insulating layer positioned between said stress layer and said strained layer.